MSP430FR2433硬件IIC读取HDC1080 数据始终为0x00？

#include “include.h”

#define HDC1080_I2C_ADDR 0x80
#define HDC1080_Temperature 0x00
#define HDC1080_Humidity 0x01
#define HDC1080_Configuration 0x02
#define HDC1080_Manufacturer_ID 0xFE
#define HDC1080_Device_ID 0xFF

#define Manufacturer_ID_value 0x5449
#define Device_ID_value 0x1050
#define Configuration_1 0x1000
#define Configuration_2 0x3000

#define CMD_TYPE_0_SLAVE 0
#define CMD_TYPE_1_SLAVE 1
#define CMD_TYPE_2_SLAVE 2

#define CMD_TYPE_0_MASTER 3
#define CMD_TYPE_1_MASTER 4
#define CMD_TYPE_2_MASTER 5

#define TYPE_0_LENGTH 1
#define TYPE_1_LENGTH 2
#define TYPE_2_LENGTH 6

#define MAX_BUFFER_SIZE 20

uint8_t SlaveType2 [MAX_BUFFER_SIZE] = {0};
uint8_t SlaveType1 [MAX_BUFFER_SIZE] = {0};
uint8_t SlaveType0 [MAX_BUFFER_SIZE] = {0};

typedef enum I2C_ModeEnum{
IDLE_MODE,
NACK_MODE,
TX_REG_ADDRESS_MODE,
RX_REG_ADDRESS_MODE,
TX_DATA_MODE,
RX_DATA_MODE,
SWITCH_TO_RX_MODE,
SWITHC_TO_TX_MODE,
TIMEOUT_MODE
} I2C_Mode;
I2C_Mode MasterMode = IDLE_MODE;

uint8_t TransmitRegAddr = 0;

uint8_t ReceiveBuffer[MAX_BUFFER_SIZE] = {0};
uint8_t RXByteCtr = 0;
uint8_t ReceiveIndex = 0;
uint8_t TransmitBuffer[MAX_BUFFER_SIZE] = {0};
uint8_t TXByteCtr = 0;
uint8_t TransmitIndex = 0;

I2C_Mode I2C_Master_WriteReg(uint8_t dev_addr, uint8_t reg_addr, uint8_t *reg_data, uint8_t count);
I2C_Mode I2C_Master_ReadReg(uint8_t dev_addr, uint8_t reg_addr, uint8_t count);
void CopyArray(uint8_t *source, uint8_t *dest, uint8_t count);

I2C_Mode I2C_Master_ReadReg(uint8_t dev_addr, uint8_t reg_addr, uint8_t count)
{
/* Initialize state machine */
MasterMode = TX_REG_ADDRESS_MODE;
TransmitRegAddr = reg_addr;
RXByteCtr = count;
TXByteCtr = 0;
ReceiveIndex = 0;
TransmitIndex = 0;

/* Initialize slave address and interrupts */
UCB0I2CSA = dev_addr;
UCB0IFG &= ~(UCTXIFG + UCRXIFG);         // Clear any pending interrupts
UCB0IE &= ~UCRXIE;                       // Disable RX interrupt
UCB0IE |= UCTXIE;                        // Enable TX interrupt

UCB0CTLW0 |= UCTR + UCTXSTT;             // I2C TX, start condition
__bis_SR_register(GIE);              // Enter LPM0 w/ interrupts

return MasterMode;

}

I2C_Mode I2C_Master_WriteReg(uint8_t dev_addr, uint8_t reg_addr, uint8_t reg_data, uint8_t count)
{
/ Initialize state machine */
MasterMode = TX_REG_ADDRESS_MODE;
TransmitRegAddr = reg_addr;

//Copy register data to TransmitBuffer
CopyArray(reg_data, TransmitBuffer, count);

TXByteCtr = count;
RXByteCtr = 0;
ReceiveIndex = 0;
TransmitIndex = 0;

/* Initialize slave address and interrupts */
UCB0I2CSA = dev_addr;
UCB0IFG &= ~(UCTXIFG + UCRXIFG);       // Clear any pending interrupts
UCB0IE &= ~UCRXIE;                       // Disable RX interrupt
UCB0IE |= UCTXIE;                        // Enable TX interrupt

UCB0CTLW0 |= UCTR + UCTXSTT;             // I2C TX, start condition
__bis_SR_register(GIE);              // Enter LPM0 w/ interrupts

return MasterMode;

}

void CopyArray(uint8_t *source, uint8_t *dest, uint8_t count)
{
uint8_t copyIndex = 0;
for (copyIndex = 0; copyIndex < count; copyIndex++)
{
dest[copyIndex] = source[copyIndex];
}
}

void initGPIO()
{
// I2C pins
P1SEL0 |= BIT2 | BIT3;

// Disable the GPIO power-on default high-impedance mode to activate
// previously configured port settings
PM5CTL0 &= ~LOCKLPM5;

}

void initClockTo16MHz()
{
// Configure one FRAM waitstate as required by the device datasheet for MCLK
// operation beyond 8MHz before configuring the clock system.
FRCTL0 = FRCTLPW | NWAITS_1;

// Clock System Setup
__bis_SR_register(SCG0);                           // disable FLL
CSCTL3 |= SELREF__REFOCLK;                         // Set REFO as FLL reference source
CSCTL0 = 0;                                        // clear DCO and MOD registers
CSCTL1 &= ~(DCORSEL_7);                            // Clear DCO frequency select bits first
CSCTL1 |= DCORSEL_5;                               // Set DCO = 16MHz
CSCTL2 = FLLD_0 + 487;                             // DCOCLKDIV = 16MHz
__delay_cycles(3);
__bic_SR_register(SCG0);                           // enable FLL
while(CSCTL7 & (FLLUNLOCK0 | FLLUNLOCK1));         // FLL locked

}

void initI2C()
{
UCB0CTLW0 = UCSWRST; // Enable SW reset
UCB0CTLW0 |= UCMODE_3 | UCMST | UCSSEL__SMCLK | UCSYNC; // I2C master mode, SMCLK
UCB0BRW = 160; // fSCL = SMCLK/160 = ~100kHz
UCB0I2CSA = HDC1080_I2C_ADDR; // Slave Address
UCB0CTLW0 &= ~UCSWRST; // Clear SW reset, resume operation
UCB0IE |= UCTXIE0 | UCRXIE0 | UCNACKIE;
}

//******************************************************************************
// Main ************************************************************************
// Send and receive three messages containing the example commands *************
//******************************************************************************

int main(void) {
WDTCTL = WDTPW | WDTHOLD; // Stop watchdog timer
initClockTo16MHz();
initGPIO();
initI2C();
Usart_Init();
// I2C_Master_WriteReg(HDC1080_I2C_ADDR, Configuration, Configuration_1, TYPE_0_LENGTH);

printf("BEFORE:%x\r\n",ReceiveBuffer[0]);

I2C_Master_ReadReg(HDC1080_I2C_ADDR, HDC1080_Manufacturer_ID, MAX_BUFFER_SIZE);
CopyArray(ReceiveBuffer, SlaveType0, TYPE_0_LENGTH);
printf("AFTER:%x\r\n",ReceiveBuffer[0]);

__bis_SR_register(GIE);
return 0;

}

//******************************************************************************
// I2C Interrupt ***************************************************************
//******************************************************************************

#if defined(TI_COMPILER_VERSION) || defined(IAR_SYSTEMS_ICC)
#pragma vector = USCI_B0_VECTOR
__interrupt void USCI_B0_ISR(void)
#elif defined(GNUC)
void attribute ((interrupt(USCI_B0_VECTOR))) USCI_B0_ISR (void)
#else
#error Compiler not supported!
#endif
{
//Must read from UCB0RXBUF
uint8_t rx_val = 0;
switch(__even_in_range(UCB0IV, USCI_I2C_UCBIT9IFG))
{
case USCI_NONE: break; // Vector 0: No interrupts
case USCI_I2C_UCALIFG: break; // Vector 2: ALIFG
case USCI_I2C_UCNACKIFG: // Vector 4: NACKIFG
break;
case USCI_I2C_UCSTTIFG: break; // Vector 6: STTIFG
case USCI_I2C_UCSTPIFG: break; // Vector 8: STPIFG
case USCI_I2C_UCRXIFG3: break; // Vector 10: RXIFG3
case USCI_I2C_UCTXIFG3: break; // Vector 12: TXIFG3
case USCI_I2C_UCRXIFG2: break; // Vector 14: RXIFG2
case USCI_I2C_UCTXIFG2: break; // Vector 16: TXIFG2
case USCI_I2C_UCRXIFG1: break; // Vector 18: RXIFG1
case USCI_I2C_UCTXIFG1: break; // Vector 20: TXIFG1
case USCI_I2C_UCRXIFG0: // Vector 22: RXIFG0
rx_val = UCB0RXBUF;
if (RXByteCtr)
{
ReceiveBuffer[ReceiveIndex++] = rx_val;
RXByteCtr–;
}

    if (RXByteCtr == 1)
    {
      UCB0CTLW0 |= UCTXSTP;
    }
    else if (RXByteCtr == 0)
    {
      UCB0IE &= ~UCRXIE;
      MasterMode = IDLE_MODE;
    }
    break;
case USCI_I2C_UCTXIFG0:                 // Vector 24: TXIFG0
    switch (MasterMode)
    {
      case TX_REG_ADDRESS_MODE:
          UCB0TXBUF = TransmitRegAddr;
          if (RXByteCtr)
          {

// MasterMode = SWITCH_TO_RX_MODE; // Need to start receiving now
UCB0IE |= UCRXIE; // Enable RX interrupt
UCB0IE &= ~UCTXIE; // Disable TX interrupt
UCB0CTLW0 &= ~UCTR; // Switch to receiver
MasterMode = RX_DATA_MODE; // State state is to receive data
UCB0CTLW0 |= UCTXSTT; // Send repeated start
if (RXByteCtr == 1)
{
//Must send stop since this is the N-1 byte
while((UCB0CTLW0 & UCTXSTT));
UCB0CTLW0 |= UCTXSTP; // Send stop condition
}
}
else
{
// MasterMode = TX_DATA_MODE; // Continue to transmision with the data in Transmit Buffer
if (TXByteCtr)
{
UCB0TXBUF = TransmitBuffer[TransmitIndex++];
TXByteCtr–;
}
else
{
//Done with transmission
UCB0CTLW0 |= UCTXSTP; // Send stop condition
MasterMode = IDLE_MODE;
UCB0IE &= ~UCTXIE; // disable TX interrupt
}
}
break;

      case SWITCH_TO_RX_MODE:
          UCB0IE |= UCRXIE;              // Enable RX interrupt
          UCB0IE &= ~UCTXIE;             // Disable TX interrupt
          UCB0CTLW0 &= ~UCTR;            // Switch to receiver
          MasterMode = RX_DATA_MODE;    // State state is to receive data
          UCB0CTLW0 |= UCTXSTT;          // Send repeated start
          if (RXByteCtr == 1)
          {
              //Must send stop since this is the N-1 byte
              while((UCB0CTLW0 & UCTXSTT));
              UCB0CTLW0 |= UCTXSTP;      // Send stop condition
          }
          break;

      case TX_DATA_MODE:
          if (TXByteCtr)
          {
              UCB0TXBUF = TransmitBuffer[TransmitIndex++];
              TXByteCtr--;
          }
          else
          {
              //Done with transmission
              UCB0CTLW0 |= UCTXSTP;     // Send stop condition
              MasterMode = IDLE_MODE;
              UCB0IE &= ~UCTXIE;                       // disable TX interrupt
              __bic_SR_register_on_exit(CPUOFF);      // Exit LPM0
          }
          break;

      default:
          __no_operation();
          break;
    }
    break;
default: break;

}
}