四选一多路器
code
mux4_1.v
`timescale 1ns/1ns
module mux4_1(
input [1:0]d1,d2,d3,d0,
input [1:0]sel,
output[1:0]mux_out
);
reg[1:0] mux_out;
//*************code***********//
always@(d1 or d2 or d3 or d0 or sel) begin
case(sel)
2'b00:begin mux_out<=d3; end
2'b01:begin mux_out<=d2; end
2'b10:begin mux_out<=d1; end
2'b11:begin mux_out<=d0; end
endcase
end
//*************code***********//
endmodule
testbench.v
`timescale 1ns/1ns
module testbench();
reg[9:0] sel_d0_d1_d2_d3;
wire[1:0] mux_out;
// A testbench
mux4_1 mux4_1(
.d1(sel_d0_d1_d2_d3[5:4]),
.d2(sel_d0_d1_d2_d3[3:2]),
.d3(sel_d0_d1_d2_d3[1:0]),
.d0(sel_d0_d1_d2_d3[7:6]),
.sel(sel_d0_d1_d2_d3[9:8]),
.mux_out(mux_out)
);
initial begin
$dumpfile("out.vcd");
$dumpvars(0, mux4_1);
end
initial begin
sel_d0_d1_d2_d3<=0;
#200 $stop;
#300 $quit;
end
always #10 sel_d0_d1_d2_d3<=sel_d0_d1_d2_d3+1;
endmodule
输出
点击自测运行后出现以下错误(未解决):
但是测试样例通过