385FINAL REVIEW之LAB7

385FINAL REVIEW之LAB7

考前晚上写的（你为啥不早点开始复习啊啊啊），防止自己走神决定边看记一些东西，写得可能比较乱大家不要介意！！

欢迎指出错误&交流~~

LAB7 IPs and SoCs

7.1 SV 中的testbench （没空看了）

DELAY TOKEN: #

7.2 实验概述

• 概括：
  Create a working NIOS II/e based SoC which performs addition from switches into LEDs
  Program must execute from SDRAM (what we will mostly use in this lab,c里面声明的变量也是存到SDRAM里) and use PIO modules wired to LEDs
  QSF文件： for pin-mapping
  Platform Designer里面生成的lab7_soc.qsys: the hardware block containing CPU and the supporting hardware (peripherals, memory, etc)，就记一下这个qsys是在platform designer里生成的吧
  Need to add an I/O constraint for SDRAM

7.3 实验DEMO要求：

• 一开始是测试让greenLED闪；

• 之后是重新写了main.c，按reset会clear accumulator，拨动switch并且按accumulate可以把switch上的值加到accumulator上，accumulator要求是表示0-255unsigned的（加到255以后会overflow），加出来的result是显示得到了LED小灯上

• 回答TA的demo问题

• INPUTS:

1. SYSTEM RESET
2. CLEAR
3. SUM

7.4 概念及重点整理

7.4.1 SoC 系统级芯片:

Motivations: All systems need lots of low performance tasks (getting data in and out of system, formatting data,
debugging, user interface). Therefore, we want to use software for lower performance tasks.

Typical component of an SoC (in lab 7):
CPU, memory, peripherals, accelerators

一些缩写和备注（有些平时做实验也没有管是什么意思的缩写今天终于知道他们的全称了orz）：

• On-Chip memory: RAM, ROM

• PIO module:

as a bridge from AVALON to FPGA logic
PIO modules may be input (to software), output (to FPGA fabric), or bidirectional.

• BSP: Board Support Package
  contains our linker script
  （source file经过compiler变成object file, object file经过linker（linker script）变成hex file）

• PLL: Phase-locked loop 锁相环，用来统一整合时钟信号(generate phase shift–lab7中使得连接到SDRAM的CLOCK相比于SDRAM Controller的clock延迟了3ns，因为controller要经过一个control logic可能会比较复杂有延时)

• IP: Intellectual Property

分为软IP、固IP和硬IP

IP（知识产权）核将一些在数字电路中常用，但比较复杂的功能块，如FIR滤波器、SDRAM控制器、PCI接口等设计成可修改参数的模块。随着CPLD/FPGA的规模越来越大，设计越来越复杂（IC的复杂度以每年55%的速率递增，而设计能力每年仅提高21%），设计者的主要任务是在规定的时间周期内完成复杂的设计。调用IP核能避免重复劳动，大大减轻工程师的负担，因此使用IP核是一个发展趋势，IP核的重用大大缩短了产品上市时间。

*虽然不是很懂但是看粗体大概明白了是啥意思

IP核有三种不同的存在形式：HDL语言形式，网表形式、版图形式。分别对应我们常说的三类IP内核：软核、固核和硬核。 ——FROM 百度百科 IP核

• RTL: Register Transfer Level，寄存器传输级 (不关注寄存器和组合逻辑的细节而通过描述寄存器-寄存器之间的逻辑功能描述电路的HDL层次)

#有缘再更系列：
.ELF file
.SDC

7.4.2 SDRAM

1. The full name of SDRAM: Synchronous Dynamic Random Access Memory 同步动态随机存储器.
   “动态”：Inside the SDRAM, the data is stored in binary by 0 and 1 through capacitors. Since the capacitors keep discharging, we need to charge them frequently, which is the exact meaning of “refreshing”.

“随机”：自由指定地址读写
2. Static RAM 比 SDRAM 快:
The downside of all of this refreshing is that it takes time and slows down the memory. This makes static RAM significantly faster than dynamic RAM.

4. 计算SDRAM的容量：BANK数目 x 行地址 x 列地址 x 数据位宽
   举例：
   该图中显示bank数目= 4，已知行地址13位（2¹³个）列地址10位（2¹⁰），data width为32bit
   则total amount of memory:
   =4x(2¹³)x(2¹⁰)x32bits=1.073e9bits
   =1.073e9/(1024x1024x8)Mbytes=128Mbytes
   =1.073e9/(1024x1024x1024)Gbit=1Gbit

Maximum theoretical transfer rate 计算：
32bits/t_ac(Access time)=32bit/5.5ns=5.18*10^9bits/s

base address: 0x10000000

7.4.3 NIOS II ISA

1. NIOS II/e: IP based 32-bit CPU which can programmed using a high-level language (in this class, we’ll be using C)
2. Use NIOS II as system controller to handle tasks like user interface, data in/outs (do not need high performance) and use accelerator peripheral designed in SV handle high performance operations.
3. <700 LEs: 使用最少的FPGA逻辑和内存资源
4. tradeoff: performance vs LEs (resource optimized)

Nios II 经济型处理器内核的逻辑元件只有 600 个，是微控制器应用的理想选择。Nios II 经济型处理器内核、软件工具和设备驱动程序均为免费提供。
https://www.intel.cn/content/www/cn/zh/products/programmable/processor/nios-ii.html

5. Configuration:
   
6. USES Modified Harvard RISC architecture

• Von Neumann architecture
  (data和instruction共用memory和bus)
  The same memory and bus are used to store both data and instructions.
  Its drawback is that the CPU is then unable to access program memory and data memory simultaneously.

• Pure Harvard architecture
  (data和instruction用自己各自的memory和bus)
  it stores the instructions and data in different memory
  unit and access them via different buses (physically separated).
  especially powerful in DSP

• Modified Harvard architecture
  the same memory space will store both instructions and data, but they are stored in different blocks (by having separate address spaces and different buses and special instructions).
  一些常值比如pi或者text string可以放在instruction memory里面，instruction也可以被read as if they were data.

• RISC VS CISC （来不及复习了就标注一下）
  RISC: Reduced Instruction Set Computing
  CISC: Complex Instruction Set Computing

7.4.3 杂杂杂

volatile unsigned int key_reset = (unsigned int)0x70;

被volatile修饰的变量能够保证每个线程能够获取该变量的最新值，从而避免出现数据脏读的现象
https://www.jianshu.com/p/157279e6efdb

DE2 board上storage elements的storage capacity：