385FINAL REVIEW之LAB8

385FINAL REVIEW之LAB8

考完final已经心死了。

LAB8 USB & VGA

8.1 实验概述

• Fill in functions in io_handler.c (lower level) and usb.c (higher level)
  These toggle the PIOs which you created to talk to the USB chip

• Create a synchronizer circuit using hpi_io_intf.sv (this makes sure there
  synchronous->asynchronous transitions between the clocked NIOS II and unclocked EZ-OTG do not cause problems)

JTAG-UART

For the connection of NIOS II/e and our host computer
If this module is missing, then we cannot use our PC as host device. i.e. we would not be able to type in message and key on the keyboard on our PC and let NIOS ii use it via scanf(), etc.

USB

USB Port has 4 pins
DE2-115 board comes with the Cypress EZ-OTG (CY7C67200) USB controller
– Can make DE2-115 act as a host or a USB device
For this lab, we will use USB host mode
OTG_DATA should be high Z (tristated) when NIOS is not writing to OTG_DATA inout bus.

USBRead: 1) io_write; 2) io_read:
USBWrite: 1) io_write: 2) io_write:

This function writes data to the internal registers of the Cypress CY7C67200 USB controller.
– First set address register (0b10) to address (in EZ-OTG memory space)
– Set data register (0b00) with data to be written

This function reads data from the internal registers of the Cypress CY7C67200 USB controller.
– First set address register (0b10) to address (in EZ-OTG memory space)
– Read data out of data register (0b00)

hpi_io_intf.sv

works as the interface between NIOS II and EZ-OTG chip
hpi_io_intf.sv acts as a buffer, adding one cycle of delay on the output
– This ensures there are no glitches from synchronous FPGA logic to asynchronous HPI
interface

Q: if we don’t have the tristate buffer in hpi_io_intf:
A:

An inout logic must be connected to a tristate buffer, otherwise the behavior is undefined.

VGA

Screen refresh rate = 60 Hz
One frame = 16.67 ms
Overall pixel frequency = 25.175 MHz

Horizontal timing:
HS Pulse: Active Low for most monitors

VGA Controller: produces the synchronization signal of both horizontal and vertical direction

Drawing

• Fixed Function
• Frame Buffer

On-Chip Memory

When we talk about on chip memory it means when the processor needs some data, instead of fetching it from main memory it fetches it from some component that is installed on processor itself. The data that a processor frequently needs is prefetched from memory to SRAM to decrease the delay or the latency. SRAM is used as on chip storage.

SRAM, SDRAM

SRAM does not need constant updates, its access speed range is faster than SDRAM

REFERENCE: UIUC ECE385 LECTURE9