使用iverilog设计一个110110111序列检测器

module seq9_detect_mealy(x,clk, y);
// Mealy machine for a three-1s sequence detection
    input x, clk;
    output y;
    reg y;
    reg [3:0] state=4'b0101; //present and next states
    parameter S0=4'b0101,S1=4'b1101,S2=4'b1001,S3=4'b1111,S4=4'b0111,
              S5=4'b1100,S6=4'b0100,S7=4'b0001,S8=4'b1000;
// Next state and output combinational logic
// Use blocking assignments "="
always @(posedge clk)
case (state)
        S0: if (x) begin state = S1; y = 0; end
    	else begin state = S0; y = 0; end
	S1: if (x) begin state = S2; y = 0; end
	else begin state = S0; y = 0; end
	S2: if (x) begin state = S2; y = 0; end
	else begin state = S3; y = 0; end
	S3: if (x) begin state = S4; y = 0; end
	else begin state = S0; y = 0; end
	S4: if (x) begin state = S5; y = 0; end
	else begin state = S0; y = 0; end
	S5: if (x) begin state = S2; y = 0; end
	else begin state = S6; y = 0; end
	S6: if (x) begin state = S7; y = 0; end
	else begin state = S0; y = 0; end
	S7: if (x) begin state = S8; y = 0; end
	else begin state = S0; y = 0; end
	S8: if (x) begin state = S2; y = 1; end
	else begin state = S6; y = 0; end
endcase
// Sequential logic, use nonblocking assignments "<="
endmodule

或者

module seq9_detect_mealy(x,clk, y);
// Mealy machine for a three-1s sequence detection
    input x, clk;
    output y;
    reg y;
    reg [3:0] pstate=4'b0101, nstate=4'b0101; //present and next states
    parameter S0=4'b0101,S1=4'b1101,S2=4'b1001,S3=4'b1111,S4=4'b0111,
              S5=4'b1100,S6=4'b0100,S7=4'b0001,S8=4'b1000;
// Next state and output combinational logic
// Use blocking assignments "="
always @(x or pstate)
case (pstate)
        S0: if (x) begin nstate = S1; y = 0; end
    	else begin nstate = S0; y = 0; end
	S1: if (x) begin nstate = S2; y = 0; end
	else begin nstate = S0; y = 0; end
	S2: if (x) begin nstate = S2; y = 0; end
	else begin nstate = S3; y = 0; end
	S3: if (x) begin nstate = S4; y = 0; end
	else begin nstate = S0; y = 0; end
	S4: if (x) begin nstate = S5; y = 0; end
	else begin nstate = S0; y = 0; end
	S5: if (x) begin nstate = S2; y = 0; end
	else begin nstate = S6; y = 0; end
	S6: if (x) begin nstate = S7; y = 0; end
	else begin nstate = S0; y = 0; end
	S7: if (x) begin nstate = S8; y = 0; end
	else begin nstate = S0; y = 0; end
	S8: if (x) begin nstate = S2; y = 1; end
	else begin nstate = S6; y = 0; end
endcase
// Sequential logic, use nonblocking assignments "<="
always @(posedge clk)
pstate <= nstate;
endmodule

在前面的基础上已经得到相应的状态分配表，按着状态表即可写出相应的程序。上面两个程序都可以起到110110111序列检测的功能。最后是在digital上实现的，具体步骤如下：

首先，打开digital找到External

然后，放入代码，将语言调成iverilog，进行check，没有问题就模拟好了，接下来运行就可以了。