verilog 8位计数器

基于状态机的思想，实现8位计数器

verilog代码

module jsq8(clk,clr,z,qout);
input clk,clr; output reg z; output reg[2:0] qout;
always @(posedge clk or posedge clr) 		//此过程定义状态转换
begin	if(clr) qout<=0;              		//异步复位
		else  case(qout)
		3'b000: qout<=3'b001;
		3'b001: qout<=3'b010;
		3'b010: qout<=3'b011;
		3'b011: qout<=3'b100;
		3'b100: qout<=3'b101;
		3'b101: qout<=3'b110;
		3'b110: qout<=3'b111;
		3'b111: qout<=3'b000;
		default: qout<=3'b000;	/*default语句*/
		endcase
end
always @(qout) 				/*此过程产生输出逻辑*/
begin  case(qout)
		3'b100: z=1'b1;
		default:z=1'b0;
endcase
end
endmodule

testbench文件

`timescale 1 ns/ 1 ps
module jsq8_vlg_tst();
// constants                                           
// general purpose registers
reg eachvec;
// test vector input registers
reg clk;
reg clr;
                                          
wire [2:0]  qout;
wire z;
                       
jsq8 i1 (   
	.clk(clk),
	.clr(clr),
	.qout(qout),
	.z(z)
);
initial                                                
fork    
clr=1;clk=0;                                         
#5 clr=1;
#15 clr=0;
join
always
begin
#10 clk=~clk;               
end                                                    
endmodule

仿真图片（十进制显示）