9.6 16道题

1.3 4:1 mux ==》8 input and

2.divide and conquer 

• 3. Test bench architecture blocks.(asked to write a generalized code to implement gen and bfm)

4.Implement Linked list in hardware 

1.Address store in fifo

2.Data store in SRAM mem array

5. You should start by verifying each module in your DUT, starting at the bottom-most level, and work your way up to the top. You should maximize code coverage by introducing either exhaustive or random stimuli.

6. constarint

7. How would you verify a write-back 4-way set associative cache using assembly language programming.

8. Write SV assertion for a req/ack protocol

bit req, ack, clk; 

sequence s_req req;

 endsequence 

sequence s_ack ack;

 endsequence 

property ack_after_req;

 @(posedge clk) s_req |->

 ##[1:2] s_ack; //change the [1:2] accordingly 

endproperty

 assert property (ack_after_req) 

$display("ack is within [1:2] after reset");

int rand（）;

9.review cmos！

1.SRAM

2.power/leakage/delay

10.review perl

done

11.review async fifo

done

12.leetcode第一道

383

13.leetcode 第二道

414 

刷easy

14.leetcode 第三道

434

1.触及seg

2.进入循环

3.flag 拉起

4.指针猛加

5.check flag

6.cnt+1

7.指针猛加

15.leetcode 第四道

482

s=s.replace(‘-’, ’’)

这个解法妙

16.leetcode 第五道

485 done, 目前观测，for和while，没有区别，如果需要index，range（len）是好的

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https://www.glassdoor.com/Interview/california-design-verification-interview-questions-SRCH_IL.0,10_IS2280_KO11,30_IP10.htm

以上是glassdoor的dv ca问题

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