【verilog学习】Verilog语言中的或（|和||）

一、|和||的区别
|是按位或：将 a 的每个位与 b 相同的位进行相或（单个）

||是逻辑或：a 或上 b，如果a或者b有一个为1，a||b结果为1，表示真。（整体）

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题目：Build a circuit that has two 3-bit inputs that computes the bitwise-OR of the two vectors, the logical-OR of the two vectors, and the inverse (NOT) of both vectors. Place the inverse of b in the upper half of out_not (i.e., bits [5:3]), and the inverse of a in the lower half.

 解答:

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);
    assign out_or_bitwise = a|b;
    assign out_or_logical = a||b;
    assign out_not = {~b,~a};
endmodule