2021-04-20

XC7A35T-1CSG324C FPGA，BIT，vivado+modelsim,verilog
OK， today I will finish a easy task of numeric display with vivado, even it’s the first homework, I can’t do the experiment without the testbench, two of my classmates came to ask me for help, the problem is that: they don’t understand the errors appeared in their vivado, and the error stopped their synthesis step. actually, at the beginning when I was about to finishing the encoder(the former work), it cost me 1 day to debug. if you don’t know how to write a testbench and use it when you run simulation, if will require you to find out the error in the synthesis or implementation step, that’s a waste of time. and as my own experience, some warning in the step of simulation will cause the error in the step of generate. To many of the beginner, you may be wrong with you code, and it can’t be modified if you run synthesis directly, the software won’t tell you that simple mistakes. so here I will show you how to run simulation with your design code and testbench.
In the previous blog I said I will have a video display about how to run a complete procedure of designing circuit, sorry that video can’t be upload here, maybe later I will upload it in bilibili, then cite my video here, I will finish it with some thought I got in the process.and I will list some key point I think which is important for me.
first, you know how to create a project, and with vivado we can write the verilog code, here I will start a new .v file, and I’ve had the code:

the testbench is very easy, and here I will copy the code here:

```cpp
`timescale 1ns/1ns;
module testbench;
reg LB;
reg LT;
reg RBI;
reg [3:0]data;
wire [7:0]light;
wire off;
wire cho;
initial begin
    data=4'b0000; LB=0; LT=0; RBI=1;
    forever #5 data=data+1;
    end
display x_display(.LB(LB), .LT(LT), .data(data), .RBI(RBI),.light(light), .off(off), .cho(cho));
endmodule

and the function code:

```cpp
module display(LB, LT, data, RBI,light, off, cho);
input LB;
input LT;
input [3:0]data;
input RBI;
output off;
output [7:0]light;
output cho;
reg cho;
reg off;
reg [7:0]light;
always @(*) begin 
    cho=1'b1;
    if (LB==1) begin light= 8'b00000000; off=0; end
    else if(LT==1) begin light= 8'b11111100; off =0; end
    else if(RBI==0) begin light= 8'b00000000; off=1; end
    else case(data)
    4'b0000: begin light=8'b11111100; off=0; end
    4'b0001: begin light=8'b01100000; off=0; end 
    4'b0010: begin light=8'b11011010; off=0; end
    4'b0011: begin light=8'b11110010; off=0; end
    4'b0100: begin light=8'b01100110; off=0; end 
    4'b0101: begin light=8'b10110110; off=0; end 
    4'b0110: begin light=8'b10111110; off=0; end 
    4'b0111: begin light=8'b11100000; off=0; end 
    4'b1000: begin light=8'b11111110; off=0; end
    4'b1001: begin light=8'b11110110; off=0; end
    default: begin light=8'b000000000; off=0; end
    endcase
end
endmodule

testbench is only used for sim, if I can use it to create the right waveform I want, I will go to the next step of synthesis, and before synthesis, we need to disable the file of testbench(actually I don’t know whether it will cause some defaults if you keep it opening):

that’s the result I want, then you know how to do next. the testbench is a very helpful tool for you to debug, lean to code it, it’s like some battery to run your circuit file.