module traffic(Clk_12M,Rst,LedR_1,LedG_1,LedB_1,LedR_2,LedG_2,LedB_2,led15,led16,led17);
parameter S0 = 0; //主路绿灯,支路红灯
parameter S1 = 1; //主路黄灯,支路红灯
parameter S2 = 2; //主路蓝灯,支路红灯
parameter S3 = 3; //主路黄灯,支路黄灯
parameter S4 = 4; //主路红灯,支路绿灯
parameter S5 = 5; //主路红灯,支路黄灯
parameter S6 = 6; //主路红灯,支路蓝灯
parameter S7 = 7; //主路黄灯,支路黄灯
input Clk_12M,Rst;
output LedR_1,LedG_1,LedB_1,LedR_2,LedG_2,LedB_2;
output led15,led16,led17;
reg LedR_1,LedG_1,LedB_1,LedR_2,LedG_2,LedB_2;
reg Clk_1Hz;//分频器
reg [31:0]Cnt_1Hz;//计数器
/*分频器模块*/
always@(posedge Clk_12M or negedge Rst)//频率对应的是12mhz
begin
if(!Rst)
begin
Cnt_1Hz<=1;
Clk_1Hz<=1; //分频器和计数器全部设置为初值1
end
else
begin
if(Cnt_1Hz>=6000000)//当计数器大于等于6的10的六次方
begin
Cnt_1Hz<=1;//计数器置一
Clk_1Hz<=~Clk_1Hz;//分频器取反
end
else
Cnt_1Hz<=Cnt_1Hz+1;
end
end
/*计数器模块*/
reg[7:0]Cnt60;
always@(posedge Clk_1Hz or negedge Rst)
begin
if(!Rst)
begin
Cnt60<=0;
end
else
begin
if(Cnt60>=60)
begin
Cnt60<=0;//60清零
end
else
Cnt60<=Cnt60+1;
end
end
//状态转换
reg [2:0] state;
always@(posedge Clk_12M or negedge Rst)
begin
if(!Rst)
begin
LedR_1<=0;
LedG_1<=0;
LedB_1<=0;
LedR_2<=0;
LedG_2<=0;
LedB_2<=0;
end
else
begin
case(state)
S0://主路绿灯45s,辅路红灯45s
begin
if(Cnt60<=45)
begin
LedR_1<=1;
LedG_1<=0;
LedB_1<=1;
LedR_2<=0;
LedG_2<=1;
LedB_2<=1;
end
else
state<=S1;
end
S1://主路黄灯5s,辅路红灯5s
begin
if(Cnt60<=50)
begin
LedR_1<=0;
LedG_1<=0;
LedB_1<=1;
LedR_2<=0;
LedG_2<=1;
LedB_2<=1;
end
else
state<=S2;
end
S2://主路蓝灯5s,辅路红灯5s
begin
if(Cnt60<=55)
begin
LedR_1<=1;
LedG_1<=1;
LedB_1<=0;
LedR_2<=0;
FPGA——交通灯(含有转向灯)
于 2023-07-05 22:11:08 首次发布