Nand2Tetris——project03

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已于 2024-04-27 15:36:01 修改

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分类专栏： Nand2Tetris 文章标签：硬件工程

于 2024-04-24 14:22:11 首次发布

本文链接：https://blog.csdn.net/weixin_66436494/article/details/138157692

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一、前言

项目来源：

该项目是著名课程Nand2Tetris的课程项目，总共分12部分，从零开始构建属于自己的hack计算机。该文项目属于第三个子项目。

项目路线介绍：

在硬件部分，你将进入 01 的世界，用与非门构造出逻辑电路，并逐步搭建出一个 CPU 来运行一套课程作者定义的简易汇编代码。在软件部分，你将编写一个编译器，将作者开发的一个名为Jack的高级语言编译为可以运行在虚拟机上的字节码，然后进一步翻译为汇编代码。你还将开发一个简易的 OS，让你的计算机支持输入输出图形界面。至此，你可以用 Jack 开发一个俄罗斯方块的小游戏，将它编译为汇编代码，运行在你用与非门搭建出的 CPU 上，通过你开发的 OS 进行交互。

二、项目介绍

目标：

1bit寄存器，16bit寄存器

RAM8，RAM64，RAM512，RAM4K，RAM16K
程序计数器PC
要求：使用HDL语言实现，并且通过所有芯片在硬件模拟器的测试。
细节：

运算芯片的二进制编码格式为补码
该次项目的关键在于将上一层实现的芯片模块化组装入下一个更高层的芯片，比如：16位bit寄存器由1bit寄存器堆叠起来，高容量的RAM由低容量的RAM堆叠起来
内存芯片的堆叠可以从RAM8开始研究，后面以此类推，不断加加加
与第二章最大的区别在于本章使用上的时序逻辑电路的关键——DFF芯片，使得后续芯片具有持续性

三、项目展示

1.HDL文件图

在这里插入图片描述

2.实现代码

2.1.Bit

bit芯片结构图

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/Bit.hdl

/**
 * 1-bit register:
 * If load[t] == 1 then out[t+1] = in[t]
 *                 else out does not change (out[t+1] = out[t])
 */

CHIP Bit {
    IN in, load;
    OUT out;

    PARTS:
    Mux(a=dffout,b=in,sel=load,out=Muxin);
    DFF(in=Muxin,out=dffout);
    And(a=dffout,b=true,out=out);
}

2.2.Register

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/Register.hdl

/**
 * 16-bit register:
 * If load[t] == 1 then out[t+1] = in[t]
 * else out does not change
 */

CHIP Register {
    IN in[16], load;
    OUT out[16];

    PARTS:
    Bit(in=in[0],load=load,out=out[0]);
    Bit(in=in[1],load=load,out=out[1]);
    Bit(in=in[2],load=load,out=out[2]);
    Bit(in=in[3],load=load,out=out[3]);
    Bit(in=in[4],load=load,out=out[4]);
    Bit(in=in[5],load=load,out=out[5]);
    Bit(in=in[6],load=load,out=out[6]);
    Bit(in=in[7],load=load,out=out[7]);
    Bit(in=in[8],load=load,out=out[8]);
    Bit(in=in[9],load=load,out=out[9]);
    Bit(in=in[10],load=load,out=out[10]);
    Bit(in=in[11],load=load,out=out[11]);
    Bit(in=in[12],load=load,out=out[12]);
    Bit(in=in[13],load=load,out=out[13]);
    Bit(in=in[14],load=load,out=out[14]);
    Bit(in=in[15],load=load,out=out[15]);
}

2.3.RAM8

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/RAM8.hdl

/**
 * Memory of 8 registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM8 {
    IN in[16], load, address[3];
    OUT out[16];

    PARTS:
       DMux8Way(in=load,sel=address,a=load0,b=load1,c=load2,d=load3,e=load4,f=load5,g=load6,h=load7);
   Register(in=in,load=load0,out=out0);
   Register(in=in,load=load1,out=out1);
   Register(in=in,load=load2,out=out2);
   Register(in=in,load=load3,out=out3);
   Register(in=in,load=load4,out=out4);
   Register(in=in,load=load5,out=out5);
   Register(in=in,load=load6,out=out6);
   Register(in=in,load=load7,out=out7); Mux8Way16(a=out0,b=out1,c=out2,d=out3,e=out4,f=out5,g=out6,h=out7,sel=address,out=out);
}

2.4.RAM64

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/RAM64.hdl

/**
 * Memory of 64 registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM64 {
    IN in[16], load, address[6];
    OUT out[16];

    PARTS:
    DMux8Way(in=load,sel=address[0..2],a=load0,b=load1,c=load2,d=load3,e=load4,f=load5,g=load6,h=load7);
    RAM8(in=in,load=load0,address=address[3..5],out=r0);
    RAM8(in=in,load=load1,address=address[3..5],out=r1);
    RAM8(in=in,load=load2,address=address[3..5],out=r2);
    RAM8(in=in,load=load3,address=address[3..5],out=r3);
    RAM8(in=in,load=load4,address=address[3..5],out=r4);
    RAM8(in=in,load=load5,address=address[3..5],out=r5);
    RAM8(in=in,load=load6,address=address[3..5],out=r6);
    RAM8(in=in,load=load7,address=address[3..5],out=r7);
Mux8Way16(a=r0,b=r1,c=r2,d=r3,e=r4,f=r5,g=r6,h=r7,sel=address[0..2],out=out);
}

2.5.RAM512

// This file is part of the materials accompanying the book 
// "The Elements of Computing Systems" by Nisan and Schocken, 
// MIT Press. Book site: www.idc.ac.il/tecs
// File name: projects/03/b/RAM512.hdl

/**
 * Memory of 512 registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM512 {
    IN in[16], load, address[9];
    OUT out[16];

    PARTS:
    DMux8Way(in=load,sel=address[0..2],a=load0,b=load1,c=load2,d=load3,e=load4,f=load5,g=load6,h=load7);
    RAM64(in=in,load=load0,address=address[3..8],out=out0);
    RAM64(in=in,load=load1,address=address[3..8],out=out1);
    RAM64(in=in,load=load2,address=address[3..8],out=out2);
    RAM64(in=in,load=load3,address=address[3..8],out=out3);
    RAM64(in=in,load=load4,address=address[3..8],out=out4);
    RAM64(in=in,load=load5,address=address[3..8],out=out5);
    RAM64(in=in,load=load6,address=address[3..8],out=out6);
    RAM64(in=in,load=load7,address=address[3..8],out=out7);
    Mux8Way16(a=out0,b=out1,c=out2,d=out3,e=out4,f=out5,g=out6,h=out7,sel=address[0..2],out=out);
    }

2.6.RAM4K

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM4K.hdl

/**
 * Memory of 4K registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM4K {
    IN in[16], load, address[12];
    OUT out[16];

    PARTS:  DMux8Way(in=load,sel=address[0..2],a=load0,b=load1,c=load2,d=load3,e=load4,f=load5,g=load6,h=load7);
    RAM512(in=in,load=load0,address=address[3..11],out=out0);
    RAM512(in=in,load=load1,address=address[3..11],out=out1);
    RAM512(in=in,load=load2,address=address[3..11],out=out2);
    RAM512(in=in,load=load3,address=address[3..11],out=out3);
    RAM512(in=in,load=load4,address=address[3..11],out=out4);
    RAM512(in=in,load=load5,address=address[3..11],out=out5);
    RAM512(in=in,load=load6,address=address[3..11],out=out6);
    RAM512(in=in,load=load7,address=address[3..11],out=out7);
Mux8Way16(a=out0,b=out1,c=out2,d=out3,e=out4,f=out5,g=out6,h=out7,sel=address[0..2],out=out);
}

2.7.RAM16K

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/b/RAM16K.hdl

/**
 * Memory of 16K registers, each 16 bit-wide. Out holds the value
 * stored at the memory location specified by address. If load==1, then 
 * the in value is loaded into the memory location specified by address 
 * (the loaded value will be emitted to out from the next time step onward).
 */

CHIP RAM16K {
    IN in[16], load, address[14];
    OUT out[16];

    PARTS:
    DMux4Way(in=load,sel=address[0..1],a=load0,b=load1,c=load2,d=load3);
    RAM4K(in=in,load=load0,address=address[2..13],out=out0);
    RAM4K(in=in,load=load1,address=address[2..13],out=out1);
    RAM4K(in=in,load=load2,address=address[2..13],out=out2);
    RAM4K(in=in,load=load3,address=address[2..13],out=out3);
    Mux4Way16(a=out0,b=out1,c=out2,d=out3,sel=address[0..1],out=out);

}

2.8.PC

// This file is part of www.nand2tetris.org
// and the book "The Elements of Computing Systems"
// by Nisan and Schocken, MIT Press.
// File name: projects/03/a/PC.hdl

/**
 * A 16-bit counter with load and reset control bits.
 * if      (reset[t] == 1) out[t+1] = 0
 * else if (load[t] == 1)  out[t+1] = in[t]
 * else if (inc[t] == 1)   out[t+1] = out[t] + 1  (integer addition)
 * else                    out[t+1] = out[t]
 */

CHIP PC {
    IN in[16],load,inc,reset;
    OUT out[16];

    PARTS:
    Inc16(in=reout,out=incout);
    Mux16(a=reout,b=incout,sel=inc,out=mux01);
    Mux16(a=mux01,b=in,sel=load,out=mux02);
    Mux16(a=mux02,b=false,sel=reset,out=muxout);
    Register(in=muxout,load=true,out=reout);
    Or16(a=reout,b=reout,out=out);
}

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Nand2Tetris——project03

项目来源：该项目是著名课程Nand2Teris的课程项目，总共分12部分，从零开始构建属于自己的hack计算机。该文项目属于第三个子项目。项目路线介绍：在硬件部分，你将进入 01 的世界，用与非门构造出逻辑电路，并逐步搭建出一个 CPU 来运行一套课程作者定义的简易汇编代码。在软件部分，你将编写一个编译器，将作者开发的一个名为Jack的高级语言编译为可以运行在虚拟机上的字节码，然后进一步翻译为汇编代码。你还将开发一个简易的 OS，让你的计算机支持输入输出图形界面。
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