SoC Architecture Design & Verification

一、SoC Design Concepts

• SoC Architecture
• SOC Design Integration
• SoC Subsystems
• Processor, High speed, Low speed, Multimedia subsystem
• SoC Interconnects & NOCs
• NoC Overview – Types of NOCs, purpose and diagram
• SoC Digital & Analog Components
• SOC UPF
• Voltage domains
• Power domains
• Clock domains
• Different clock mode – XO mode, at-speed mode
• CDC
• SoC Address Mapping
• SoC Interrupt Mapping
• SoC Frequency Plan
• SoC Performance requirements
• SoC Features
• SoC Memories: Msg ram, Iram, DDR, Flash
• GPIO purpose : Pad muxing
• I/O’s of SOC: Dedicated IO’s, and GPIOs

二、SoC Verification Concepts

• Setting up environment
• Processor boot concepts
• Types of verification : how they are different
• SoC Processor-TB interaction
• How to set reset location to start booting.
• Loading C code into memories – Front door, back door.
• SCF file
• SoC Architecture, understanding transaction matrix
• SOC Test bench architecture
• SoC environment structure
• Setting up SOC TB environment
• Using library functions to implement C test cases
• Integrating UVC in Testbench setup
• sequence usage in SV testcase
• understanding handshake between Native & SV code
• Functional Verification
• Formal Verification (Connectivity Checks)
• SOC Test plan
• SOC Test case Flow
• SOC Test case Coding (C files & SV files)
• DDR initialization
• Setting up regression
• Running test cases & regression
• SOC Test debug
• Verification closure
• Power Aware Simulations

三、SoC Test Plan

• Listing down test requirements, pass criteria
• Functional test
• register wr-rd, reset tests
• Interrupt tests
• targeting different frequency plans
• Feature(use-case) tests
• power aware tests
• Fuse tests
• End to end data transfer tests
• Booting from different memories
• Address decoding access tests
• Connectivity tests
• Power collapse and uncollapse tests
• SOC testcase bring up
• Memory preloading
• Processor booting from different memories
• TIC mode
• PLL locking(LMN values)
• Functional mode
• Power domains to be up
• clock domains to be up, required frequencies
• Understanding required flow to implement testcase
• Device Initialisation
• DDR initialisation
• Enabling DDR access to different processors
• Processor boot sequence
• Processor boot from different memories
• C test Main function
• Interrupt handler

四、Debugging Tests

• tarmac log
• List file
• mpf file
• Simulation log
• Wave dump debug
• Message based debug
• Warnings, errors

五、Typical Testcase Issues

• Processor not booting
• register looping
• Not working at current frequency plan
• pll not locked
• Memory not preloaded
• clocks not running
• Access is not enabled to register or memory space
• Simulation not proceeding in time
• Simulation is proceeding in time but not completing (looping)
• Interrupt not serviced
• interrupt not generated
• Signal not sampled
• sub module functional issues
• Denali errors
• Memory loading ‘x’ debug
• tied signals, unconnected ports
• Cycle slips

六、SoC Gate Level Simulations

• Choosing tests for GLS
• Vector generation
• EVCD generation
• Need for EVCD
• Vector runs on VT setup
• Generating binaries for running on tester
• RMA
• ECO
• What stage ECO is issued
• Vector debug
• Significance
• Format
• Vector runs on VT setup
• Production vectors
• Characterization vectors
• RMA

七、SoC Base Lines

• Design baseline
• Updating env for custom baseline
• all design sub component latest baselines
• verif baseline

八、Running Testcases & Regression

• Command line
• sim_gui mode
• Command line options
• using force files, timing corners, frequency plans

九、Low Power Verification

• UPF
• PA RTL simulations
• PA GLS simulations

十、Vectors Runs

• Vector evcd generation
• VT simulations on testers
• Post silicon validation

十一、Verification Closure

• Regression 100% pass
• 100% toggle coverage
• reviews high level & low level
• Performance requirements
• Power requirements met