1. Undrer S3C6410, Setting ARM cpu frequency 667MHz
Because default freqency is 532MHz.
6410 CPU can run up to 667MHz, modiry Linux kernel source code:
I setting register "APLL_CON / MPLL_CON" according to S3C6410X.pdf manual, page 141, 142.
The output frequency is calculated using the following equation:
FOUT = MDIV X FIN / (PDIV X 2SDIV)
2. Then compile new kernel image, run it.
[root@EmbedSky /]# cat /proc/cpuinfo
Processor : ARMv6-compatible processor rev 6 (v6l)
BogoMIPS : 665.19
Features : swp half thumb fastmult vfp edsp java
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x0
CPU part : 0xb76
CPU revision : 6
Hardware : SMDK6410
Revision : 0000
Serial : 0000000000000000
[root@EmbedSky /]#
Because default freqency is 532MHz.
6410 CPU can run up to 667MHz, modiry Linux kernel source code:
/* arch/arm/plat-s3c64xx/s3c6400-clock.c */
void __init_or_cpufreq s3c6400_setup_clocks(void)
{
/* ... */
__raw_writel((__raw_readl(S3C_APLL_CON) & 0xfc00ffff) | (0x14d <<16), S3C_APLL_CON); /* wenxy test, 333*2 MHz */
apll = s3c6400_get_pll(xtal, __raw_readl(S3C_APLL_CON));
printk(KERN_INFO "Wenxy: S3C_APLL_CON value: 0x%x\n", (unsigned int)__raw_readl(S3C_APLL_CON));
fclk = apll / GET_DIV(clkdiv0, S3C6410_CLKDIV0_ARM);
printk(KERN_INFO "S3C64XX: PLL settings, A=%ld, M=%ld, E=%ld\n",
apll, mpll, epll);
/* ... */
}
I setting register "APLL_CON / MPLL_CON" according to S3C6410X.pdf manual, page 141, 142.
The output frequency is calculated using the following equation:
FOUT = MDIV X FIN / (PDIV X 2SDIV)
2. Then compile new kernel image, run it.
[root@EmbedSky /]# cat /proc/cpuinfo
Processor : ARMv6-compatible processor rev 6 (v6l)
BogoMIPS : 665.19
Features : swp half thumb fastmult vfp edsp java
CPU implementer : 0x41
CPU architecture: 7
CPU variant : 0x0
CPU part : 0xb76
CPU revision : 6
Hardware : SMDK6410
Revision : 0000
Serial : 0000000000000000
[root@EmbedSky /]#