目录
3.2.3 配置IN_EN Register:(Offset = 1Bh)
3.2.4 配置CS_SELECT Register: (Offset = 1Ch)
3.2.5 配置WC_CFG0/WC_CFG1 Register: (Offset = 1Dh)
3.2.6 配置Mode Register: (Offset = 32h)
3.2.7 配置Config Register: (Offset = 1Ah)
3.2.8 配置THRES_COMP Register (Offset = 21h)
3.2.9 配置THRES_CFG0~THRES_CFG4 Register(Offset = 29h)
3.2.10 配置THRESMAP_CFG2 Register(Offset = 30h)
3.2.11 配置Matrix Register (Offset = 31h)
3.2.12 配置INT_EN_COMP1/2 Register
3.2.13 配置INT_EN_CFG1/2/3/4 Register
主要是基础介绍。
一. datasheet中的相关介绍
这个芯片有24路,可以用来检测每一路的通断状态(也可以说是高低电平),也可以用来测试ADC。MCU检测高低电平是再平常不过的事,但是这样一个芯片就可以检测24路,检测结果通过SPI通讯到MCU,所以极大减少了MCU的引脚需求。
这个芯片的复位方式有三种:上电复位,硬件复位,和软件复位(硬件和软件请自行查阅说明书),芯片每一次上电都会复位一次,所有的寄存器全部回到默认值。所以这个芯片的寄存器是没有记忆功能的,每次上电的时候都要对他的寄存器进行配置。
8 Detailed Description
8.1 Overview
The TIC12400 is an advanced 24-input Multiple Switch Detection Interface (MSDI) device designed to detect external mechanical switches status in an industrial system by acting as an interface between the switches and the low-voltage microcontroller. The TIC12400 is an integrated solution that replaces many discrete components and provides integrated protection, input serialization, and system wake-up capability.
The device monitors 14 switches to GND and 10 additional switches that can be programmed to be connected to either GND or VSUPPLY. It features SPI interface to report individual switch status and provides programmability to control the device operation. The TIC12400 features a 10-bit ADC, which is useful to monitor analog inputs, such as resistor coded switches, that have multiple switching positions. To monitor only digital switches, an integrated comparator can be used instead to monitor the input status. The device has 2 modes of operation: continuous mode and polling mode.(它具有SPI接口来报告单个开关状态,并提供可编程性来控制设备的操作。TIC12400具有一个10bit的ADC,这对于监控模拟输入非常有用,例如具有多个开关位置的电阻编码开关。为了只监控数字开关,可以使用集成比较器来监控输入状态。该设备有两种运行模式:连续模式和轮询模式。) The polling mode is a low-power mode that can be activated to reduce current drawn in the system by only turning on the wetting current for a small duty cycle to detect switch status changes. An interrupt is generated upon detection of switch status change and it can be used to wake up the microcontroller to bring the entire system back to operation.
8.3.8.1 Input Current Source/Sink Selection
Among the 24 inputs, IN10 to IN23 are intended for monitoring only ground-connected switches and are connected to current sources. IN0 to IN9 can be programmed to monitor either ground-connected switches or supply-connected switches by configuring the CS_SELECT register. The default configuration of the IN0-IN9 inputs after POR is to monitor ground-connected switches (current sources are selected). To set an input to monitor supply-connected switches, set the corresponding bit to logic 1.
在24个输入中,IN10到IN23仅用于监测接地开关,并连接到电流源。通过配置CS_SELECT寄存器,可以对IN0到IN9进行编程,以监控接地开关或电源连接的开关。POR后IN0-IN9输入默认配置为监控接地开关(选择电流源)。要设置一个输入来监控电源连接的开关,请将相应的位设置为逻辑1。
8.3.8.2 Input Mode Selection
The TIC12400 has a built-in ADC and a comparator that can be used to monitor resistor coded switches or digital switches. Digital switch inputs have only two states, either open or closed, and can be adequately detected by a comparator. Resistor coded switches may have multiple positions that need to be detected, and an ADC is appropriate to monitor the different states. Each input of the TIC12400 can be individually programmed to use either a comparator or an ADC by configuring the appropriate bits in theMODE register depending on the knowledge of the external switch connections. The benefit of using a comparator instead of an ADC to monitor digital switches is its reduced polling time, which translates to overall power saving when the device operates in the low-power polling mode.
Comparator input mode is selected by default for all enabled inputs upon device reset.
该TIC12400有一个内置的ADC和一个比较器,可用于监测电阻编码开关或数字开关。数字开关输入只有两种状态,打开或关闭,可以由比较器充分监测。电阻编码开关可能有多个需要检测的位置,ADC适合于监测不同的状态。根据外部开关连接的知识,通过在mode寄存器中配置适当的位,可以对TIC12400的每个输入进行单独编程,以使用比较器或ADC。使用比较器而不是ADC来监视数字开关的好处是它减少了轮询时间,当设备在低功耗轮询模式下运行时,这将转化为整体节能。
在设备复位时,所有启用的输入默认选择比较器输入模式。
8.3.8.3 Input Enable Selection
The TIC12400 provides switch status monitoring for up to 24 inputs, but there might be circumstances in which not all inputs need to be constantly monitored. The microcontroller may choose to enable/disable monitoring of certain inputs by configuring the IN_EN register.
TIC12400为多达24个输入提供开关状态监控,但在某些情况下,可能不需要对所有输入进行持续监控。微控制器可以通过配置IN_EN寄存器来选择启用/禁用对某些输入的监控。
8.3.8.4 Thresholds Adjustment
When an input is configured as comparator input mode, the threshold level for interrupt generation of can be programmed by setting the THRES_COMP register. The threshold level settings can be set to for each individual input groups and each group consist of 4 inputs. Four threshold levels are available: 2V, 2.7V, 3V, and 4V.
When an input is configured as ADC input mode, the threshold level for interrupt generation can be configured, up to 1023 different levels, by setting the THRES_CFG1 to THRES_CFG2 registers. One threshold level can be programmed individually for each of the input from IN0 to IN11. Additionally, one common threshold, shared between inputs IN0 to IN11, can be programmed by configuring the THRES_COM bits in register MATRIX.(此外,可以通过配置寄存器MATRIX中的THRES_COM位来编程一个公共阈值,在输入IN0到IN11之间共享)。 The common threshold acts independently from the threshold THRES0 to THRES7. Inputs IN12 to IN17 use 2 preset threshold levels (THRES2A and THRES2B). Inputs 18 to 22 use 3 preset threshold levels (THRES3A, THRES3B, and THRES3C). Input 23 uses 5 preset threshold levels (THRES3A, THRES3B, THRES3C, THRES8 and THRES9).
When multiple threshold settings are used for ADC inputs, the thresholds levels needs to be configured properly.
Use the rules below (see Table 2) when setting up the threshold levels:
二. SPI相关知识
2.1 基础知识
首先说明一点,latch = read = sample,都是表示数据采样,数据有效的时刻。
SPI分主设备和从设备,两者通过SPI协议通讯。
而设置SPI的模式,是从设备的模式,决定了主设备的模式。
所以要先去搞懂从设备的SPI是何种模式,然后再将主设备的SPI的模式,设置和从设备相同的模式,即可正常通讯。
对于从设备的SPI是什么模式,有两种:
① 固定的,由SPI从设备硬件决定。
SPI从设备,具体是什么模式,相关的datasheet中会有描述,需要自己去datasheet中找到相关的描述,即:
关于SPI从设备,在空闲的时候,是高电平还是低电平,即决定了CPOL是0还是1;
然后再找到关于设备是在上升沿还是下降沿去采样数据,这样就是,在定了CPOL的值的前提下,对应的就可以推算出CPHA是0还是1了。
② 可配置的,由软件设定。
从设备也是一个SPI控制器,4种模式都支持,此时只要自己设置为某种模式即可。
然后知道了从设备的模式后,再去将SPI主设备的模式,设置为和从设备模式一样,即可。
2.2 TIC12400_SPI相关
下图是datasheet中SPI的时序图。
从中可以判断出,
SCLK空闲时是低电平0,所以CPOL = 0;
数据采样是在时钟的下降沿(第二个沿),所以CPHA = 1。
下图是SPI通信数据的读写数据格式。
如果要读取:
- 主站芯片发送的数据 bit31 需为0,bit25~bit30 是要读取的寄存器地址。(第一个方框)
- 主站芯片接收的数据 bit25~bit30 是芯片的一些状态标志位,具体可以对着说明书了解一下,bit1-bit24是从寄存器里面获取出来的值。(第二个方框)
注意一点,寄存器的有效数据是从 bit1 开始的,因为 bit0 是一个奇偶校验位。
如果是写入:
- 主站芯片发送的数据 bit31 需为1,bit25~bit30 是要写入的寄存器地址,bit1-bit24 是要写入的数据。(第三个方框)
- 主站芯片接收的数据 bit25~bit30 是芯片的一些状态标志位,bit1-bit24 是对这个寄存器数据写入之前,寄存器的数据。(第四个方框)
三. 相关寄存器配置(部分)
3.1 寄存器功能简述
1. Config Register:
选项配置寄存器,有很多使能位。注意,bit11是这个芯片的总开关,需要设1使能,芯片才能开始工作。
2. IN_EN Register
这个是每一路通道的使能开关,自己根据需求打开,默认是全部关闭的。
3. CS_SELECT Register:Current Source/Sink Selection Register
4. WC_CFG0,WC_CFG1:Wetting Current Configuration Register
5. THRES_COMP Register:Comparator Threshold Control Register
这个是高低电平的判断阈值。默认情况下是,低于2V就是对GND连接,高于2V就是高电平连接。有2V,2.7V,3V,4V。根据自己需求来。
6. THRES_CFG0 - THRES_CFG4:ADC Threshold Control Register
7. Mode Register:
配置每个引脚的模式,默认是比较模式,也可以配置为ADC模式。
暂时列这么多,不一一列出来了。
3.2 测试代码中的相关寄存器配置
3.2.1 奇偶校验位的确定
奇校验/偶校验的选择:在datasheet中会有说明。
- 奇校验:odd parity,主体数据加上校验位中的 “1” 的个数保持为奇数。
- 偶校验:even parity,主体数据加上校验位中的 “1” 的个数保持为偶数。
3.2.2 定义相关问题:(未解决)
在我们的测试代码中,首先是定义了一个:
uint8_t tx_TIC12400[4]={0U,1U,2U,3U};
定义一个4元素数组的意义是:
eg:tx_TIC12400[0] 表示的是寄存器地址;[1] [2] [3] 表示的是SPI通信序列中的第 0~23bit;
(SPI通信序列中,bit 0是奇偶校验位,在上边的[0][1][2][3]配置并组合好后,再配置奇偶检验位。)
在后续的代码中,频繁出现的有三个函数:(暂时未搞懂)
① DSPI_Deinit(INST_DSPI0); 关闭DSPI实例。
- 此功能重置DSPI外围设备,对其时钟进行选通,并禁用对内核的中断。它首先检查传输是否正在进行,如果是,则返回错误状态。
② DSPI_MasterInit(INST_DSPI0, &dspi0State, &dspi0_MasterInitConfig1); 主模式操作初始化DSPI实例。
- 此函数使用中断驱动或DMA方法传输数据。在此函数中,术语“配置”用于指示DSPI主设备正在通信的SPI设备。此函数初始化运行时状态结构以跟踪正在进行的传输,取消对DSPI模块的时钟选通,重置DSPI模块,配置IRQ状态结构,启用对内核的模块级中断,并启用DSPI模块。
③ DSPI_MasterTransferBlocking(INST_DSPI0,tx_TIC12400,rx_TIC12400,4,timeout_SPI);
- 此函数允许用户选择性地传入SPI配置结构,该结构允许用户在启动SPI传输时更改SPI总线属性。
3.2.3 配置IN_EN Register:(Offset = 1Bh)
DSPI_Deinit(INST_DSPI0);
DSPI_MasterInit(INST_DSPI0, &dspi0State, &dspi0_MasterInitConfig1);
tx_TIC12400[0]=0xB7;//IN_EN
tx_TIC12400[1]=0xFF;
tx_TIC12400[2]=0xFF;
tx_TIC12400[3]=0xFE;
解析:
8.5.2.1 Read Operation
The Read/Write bit (bit 31) of the SI bus needs to be set to logic 0 for a READ operation. The 6-bits address of the register to be accessed follows next on the SI bus. The content from bit 24 to bit 1 does not represent valid command for a read operation and will be ignored. The LSB (bit 0) is the parity bit used to detect communication errors.
8.5.2.2 Write Operation
The Read/Write bit (bit 31) on the SI bus needs to be set to 1 for a write operation. The 6-bits address of theregister to be accessed follows next on the SI bus. Note the register needs to be a writable configuration register, or otherwise, the command will be ignored. The content from bit 24 to bit 1 represents.
参照上述SPI通信数据的读写数据格式 Figure 34 可推理如下。
① Bit31:置1。
② IN_EN Register的 offset = 1Bh,即它的地址,转换成6位二进制是 011 011。
③ Data,写入24个1,使能24个通道。
④ 根据datasheet中的描述,使用奇校验。
8.3.11 Parity Check And Parity Generation
The TIC12400 uses parity bit check to ensure error-free data transmission from/to the SPI master.
The device uses odd parity, for which the parity bit is set so that the total number of ones in the transmitted data on SO (including the parity bit) is an odd number (that is, Bit0 ⊕ Bit1 ⊕ ….⊕ Bit30 ⊕ Bit31⊕ Parity = 1).
The device also does odd parity check after receiving data on SI from the SPI master. If the total number of ones in the received data (including the parity bit) is an even number, the received data is discarded. The INT will be asserted low and the PRTY_FAIL bit in the interrupt register (INT_STAT) is flagged to logic 1 to notify the host that transmission error occurred. The PRTY_FAIL flag is also asserted during SPI communications.
3.2.4 配置CS_SELECT Register: (Offset = 1Ch)
DSPI_MasterTransferBlocking(INST_DSPI0,tx_TIC12400,rx_TIC12400,4,timeout_SPI);
tx_TIC12400[0]=0xB8;//CS_SELECT
tx_TIC12400[1]=0x00;
tx_TIC12400[2]=0x03;
tx_TIC12400[3]=0xE0;
分析步骤同上。
这里是把CS_IN4 ~ CS_IN8置为 1。对应到电路图里就是IN4~IN8的5个开关输入。
3.2.5 配置WC_CFG0/WC_CFG1 Register: (Offset = 1Dh)
Wetting Current Configuration Register。
DSPI_MasterTransferBlocking(INST_DSPI0,tx_TIC12400,rx_TIC12400,4,timeout_SPI);
tx_TIC12400[0]=0xBA;//WC_CFG0
tx_TIC12400[1]=0x93;
tx_TIC12400[2]=0x6D;
tx_TIC12400[3]=0xB6;
DSPI_MasterTransferBlocking(INST_DSPI0,tx_TIC12400,rx_TIC12400,4,timeout_SPI);
tx_TIC12400[0]=0xBC;//WC_CFG1
tx_TIC12400[1]=0x1B;
tx_TIC12400[2]=0x6D;
tx_TIC12400[3]=0xA4;
分析步骤同上。
这里,对WC_CFG0 Register的配置,0-2,3-5,6-8,9-11,12-14,15-17这五组配置的是 011,对应的是WC_IN0~IN9的润湿电流为:3h = 5mA wetting current。18-20,21-23这两组配置的是 010,对应的是WC_IN10、WC_IN11的润湿电流为:2h = 2mA wetting current。
同理,对WC_CFG1 Register的配置,0-2,3-5 这两组配置的是 010,对应的是WC_IN12~IN15的润湿电流为:2h = 2mA wetting current。6-8,9-11,12-14,15-17,18-20 这五组配置的是 011,对应的是WC_IN16~IN23的润湿电流为:3h = 5mA wetting current。21bit,22bit 配置的是 0,表示AUTO_SCALE_DIS_CSO or AUTO_SCALE_DIS_CSI bit = logic 0。
wetting current:
以下是百度搜索到的:
润湿电流是电子学中用来描述电路刺穿被氧化的开关所需的能量的一种测量方法。这种氧化作用通常是通过一层薄膜故意添加的,以帮助电路闭合,而且往往是在触点上。
个人理解:就是在开关电路中,开关闭合所需的最小电流。不知道对否。
8.4.3.2 Wetting Current Auto-Scaling
The 10 mA and 15 mA wetting current settings are useful to clean oxide build-up on the mechanical switch contact surface when the switch changes state from open to close. After the switch is closed, it might be undesirable to keep the wetting current level at high level if only digital switches are monitored since it results in high current consumption and could potentially heat up the device quickly if multiple inputs are monitored. The wetting current auto-scaling feature help mitigate this issue.
When enabled (AUTO_SCALE_DIS_CSO or AUTO_SCALE_DIS_CSI bit = logic 0 in the WC_CFG1 register), wetting current is reduced to 2 mA from 10 mA or 15 mA setting after switch closure is detected. The threshold used to determine a switch closure is the threshold configured in the THRES_COMP register for inputs configured as comparator input mode. For inputs configured as ADC input mode, the threshold used to determine a switch closure depends on the input number, as described in Table 8 below:
3.2.6 配置Mode Register: (Offset = 32h)
DSPI_MasterTransferBlocking(INST_DSPI0,tx_TIC12400,rx_TIC12400,4,timeout_SPI);
tx_TIC12400[0]=0xE5;//0xE4;//Mode
tx_TIC12400[1]=0xF8;//0x00;
tx_TIC12400[2]=0x00;
tx_TIC12400[3]=0x01;
分析步骤同上。
配置结果是:Mode Register的 0~17bit为0,表示相应管脚配置为comparator mode;18~23bit为1,表示IN18~IN23管脚配置为ADC mode。
ADC mode:
3.2.7 配置Config Register: (Offset = 1Ah)
DSPI_MasterTransferBlocking(INST_DSPI0,tx_TIC12400,rx_TIC12400,4,timeout_SPI);
tx_TIC12400[0]=0xB4;//Config
tx_TIC12400[1]=0x00;
tx_TIC12400[2]=0x0A;
tx_TIC12400[3]=0xDC;
分析步骤同上。
配置结果是:no reset;POLL_TIME=8ms;POLL_ACT_TIME=512us;no CRC;DET_FILTER bit = 0h = every sample is valid and taken for threshold evaluation...等。
3.2.8 配置THRES_COMP Register (Offset = 21h)
Comparator Threshold Control Register。
DSPI_MasterTransferBlocking(INST_DSPI0,tx_TIC12400,rx_TIC12400,4,timeout_SPI);
tx_TIC12400[0]=0xC2;//THRES_COMP
tx_TIC12400[1]=0x00;
tx_TIC12400[2]=0x15;
tx_TIC12400[3]=0x54;
分析步骤同上。
配置结果是:输入通道 IN0 ~ IN23 的比较器阈值配置为 2.7V。
3.2.9 配置THRES_CFG0~THRES_CFG4 Register(Offset = 29h)
ADC Threshold Control Register。
DSPI_MasterTransferBlocking(INST_DSPI0,tx_TIC12400,rx_TIC12400,4,timeout_SPI);
tx_TIC12400[0]=0xD4;//THRES_CFG1,6.21改
tx_TIC12400[1]=0x0A;//0x07
tx_TIC12400[2]=0xA9;//0x81
tx_TIC12400[3]=0xC1;//0x55
DSPI_MasterTransferBlocking(INST_DSPI0,tx_TIC12400,rx_TIC12400,4,timeout_SPI);
tx_TIC12400[0]=0xD6;//THRES_CFG2,6.21改
tx_TIC12400[1]=0x0E;
tx_TIC12400[2]=0x62;//0x12
tx_TIC12400[3]=0xAC;//0xBC
工作相关:主要是配置 ADC 输入模式。
这里的改动有个是6.21号改的,原因是将IN18~IN23这六个复用引脚的电阻由240Ω改成了330Ω。
于是分析一下为什么这么改?
① 首先参考8.3.8.4:
Inputs 18 to 22 use 3 preset threshold levels (THRES3A, THRES3B, and THRES3C). Input 23 uses 5 preset threshold levels (THRES3A, THRES3B, THRES3C, THRES8 and THRES9).
其中的大小关系为:THRES9 ≥ THRES8 ≥ THRES3C ≥ THRES3B ≥ THRES3A
② 由下边THRESMAP_CFG2 Register寄存器的配置,和THRES_CFG1 Register 、THRES_CFG2 Register的配置,可以得出 THRES2、THRES3、THRES4、THRES5 的值。
比如:
在THRES_CFG1 Register中,0~9bit为 001 1100 000,代表THRES2的值,换为十进制是224;10~19bit是 0 1010 1010 1,代表THRES3的值,换为十进制是341。
③ 记住:输入管脚的输入端电压是6V,如下电路图所示。根据前边讲的10位ADC的电压转换关系,来计算对应的某个开关关闭后,芯片引脚处接收到的电压大小。
eg:
THRES3的十进制数是341,则对应的该阈值所代表的电压为:X ÷ 6 × 1024 = 341 ==>>推出来 X = 2V。
以此类推。
最后得出,THRES2 对应 1.3V,THRES3 对应 2V,THRES5 对应 2.7V。
2021.6.30更
请教了前辈,给出了更详细的说明。
在配置寄存器 THRES_CFG0 ~ THRES_CFG4 Register 时,实际是配置了THRES0 ~ THRES9 这10个阈值。结果如下表所示:
原(240Ω和470Ω) | 改(330Ω和470Ω) | ||
THRES_CFG0 | THRES0 | 0 | 0 |
THRES1 | 100 | 100 | |
THRES_CFG1 | THRES2 | 170 | 223 |
THRES3 | 240 | 341 | |
THRES_CFG2 | THRES4 | 367 | 342 |
THRES5 | 450 | 460 | |
THRES_CFG3 | THRES6 | 800 | 800 |
THRES7 | 1000 | 1000 | |
THRES_CFG4 (没用上) | THRES8 | 800 | 800 |
THRES9 | 1000 | 1000 |
相邻两个阈值代表一个范围,而我们要做的就是把我们要配置的值放在某个范围内,保证多个信号的传输不受影响。比如说:
未改动之前:复用管脚有两路信号,一路上边的电阻是240Ω,另一路上边是470Ω。有四种组合情况,分别是,单路240Ω、单路470Ω、双路并联156Ω、双路断开为无穷大。
然后根据公式 ,可以分别计算出四种组合情况下,不同的电阻值映射到 10bit ADC上所对应的值。
改动之后:同理。
得出下表所示:
电阻组合情况 | 在10bit ADC上的映射值(十进制) | |
改动前 | 双路闭合,并联为156Ω | 135 |
单路240Ω | 204 | |
单路470Ω | 401 | |
双路断开,为 ∞ | ||
改动后 | 双路闭合,并联为194Ω | 165 |
单路330Ω | 281 | |
单路470Ω | 401 | |
双路断开,为 ∞ |
用一个简图表示如下:
上图中,红框标注的阈值界限值,可以共用一个阈值,也可以使用两个阈值。
总的来说,就是在引脚电阻有变化时,修改上述阈值的范围值。
3.2.10 配置THRESMAP_CFG2 Register(Offset = 30h)
ADC Threshold Mapping Register。
DSPI_MasterTransferBlocking(INST_DSPI0,tx_TIC12400,rx_TIC12400,4,timeout_SPI);
tx_TIC12400[0]=0xE0;//THRESMAP_CFG2
tx_TIC12400[1]=0x00;
tx_TIC12400[2]=0x02;
tx_TIC12400[3]=0xB5;
分析步骤同上。
配置结果是:
THRESMAP_IN18_IN23_THRES3A:2h = THRES2;
THRESMAP_IN18_IN23_THRES3B:3h = THRES3;
THRESMAP_IN18_IN23_THRES3C:5h = THRES5;
3.2.11 配置Matrix Register (Offset = 31h)
3.2.12 配置INT_EN_COMP1/2 Register
Comparator Input Interrupt Generation Control Register.
3.2.13 配置INT_EN_CFG1/2/3/4 Register
ADC Input Interrupt Generation Control Register.