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原创 64-ia-32架构优化手册——目录

第一章. 略第二章. Intel(r) 64与IA-32处理器架构 2.1. SKYLATE微架构 2.1.1. 前端 2.1.2. 乱序执行引擎 2.1.3. 缓存与内存子系统 2.2. Haswell微架构 2.2.1. 前端 2.2.2. 乱序引...

2017-03-10 11:18:59 1613

原创 LLVM学习笔记——目录(含7.0更新)

前言2011年前后,GCC后端代码的阅读陷入了举步维艰的境地。GGC-3.4.6后端代码的可读性不友好(当前版本没看过,不予评价。不过据说4.0进行的重构,应该会好些),充斥着动辄数千行的函数,包含着庞大的switch块以及if块,加之函数间的相互调用,看得人昏头转向。穷极思变,转而看了一下LLVM的源代码。一撇之下,惊为天人。LLVM是第一次碰到的、几乎完全用C++开发的大规模开源项...

2017-03-10 11:14:55 6110 3

翻译 LLVM的源代码调试

原文地址:http://llvm.org/docs/SourceLevelDebugging.html#llvm-dbg-declare引子本文是与LLVM调试信息相关的所有信息的集大成者。它描述了LLVM调试信息采用的实际形式,这对哪些关心创建前端或直接处理这些信息的人是有用的。另外,本文提供了C/C++调试信息看起来像什么的具体例子LLVM调试信息背后的哲学LLVM调试信息的思

2017-03-31 13:09:40 7269

原创 LLVM学习笔记(6)

2.2.4.2. 可复用的结构2.2.4.2.1. PatFrag高级语言的特征之一是支持数据与结构的复用,TD语言也吸取了这些长处,尝试为复杂而基本的操作提供复用的可能性。这就是PatFrag(SelectionTargetDAG.td):606     class PatFrag<dag ops, dag frag, code pred = [{}],607       ...

2017-03-31 13:04:55 3981

翻译 未定义行为 != 不安全的编程

原文地址:https://blog.regehr.org/archives/1467作者:John Regehr在C与C++里,未定义行为(UB)对开发者来说是一个清晰且现实的危险,特别是当他们编写将在一个信任边界执行的代码时。一类不那么为人所知的未定义行为存在于大多数优化、领先的编译器的中间表达(IR)里。例如,除了让你一脸茫然的C形式的UB外,LLVMIR还增加了undef与poiso

2017-03-24 11:54:22 621

原创 llvm学习笔记(5)

2.2.4. 匹配模板在Instruction定义的333行,成员Pattern描述了该指令匹配怎么样的SelectionDAG结构。这是一个list类型,因此存在一条指令匹配多个dag结构的可能。在上面的例子中,这部分就是312~315行的dag。LLVM将对这样的dag生成movq2dq\t{$src, $dst|$dst, $src}形式的汇编代码(实际上,指令选择会生成一个Machin...

2017-03-24 11:51:35 3732

原创 llvm学习笔记(4)

2.2.2.2. 一般操作数寄存器以外的一般的操作数由Operand描述,它定义如下(v7.0将597行的DecoderMethod替换为bit hasCompleteDecoder = 1):593      class Operand<ValueType ty> : DAGOperand {594        ValueType Type = ty;595    ...

2017-03-22 12:19:30 2201

翻译 C编译器反证Fermat大定理

作者:JohnRegehr, Professor of Computer Science, University of Utah, USA原文地址:http://blog.regehr.org/archives/140【更新:本文没有非常清楚地解释底下的问题。我写了一篇更好的新博】。显然,我不是认真的:编译器不擅长解决高层次的数学问题,并且有很好的理由相信这个定理不能被反证。不过我

2017-03-21 11:48:40 777

翻译 64-ia-32架构优化手册(2)

2.2. Haswell微架构Haswell微架构构建在SandyBridge与IvyBridge微架构的成功之上。Haswell微架构的基本流水线功能描述在图2-2中。总之,在2.2.1-2.2.4节描述的大多数特性也适用于Broadwell微架构。Broadwell微架构的增强汇总在2.2.6节。图2-2. Haswell微架构的CPU核心流水线功能Haswell微

2017-03-17 11:42:51 850

原创 llvm学习笔记(3)

2.2.2. 参数描述Instruction定义中的OutOperandList与InOperandList分别是这样的dag:(outs op1, op2, …),(ins op1, op2, …)。Op可以是寄存器(这时通过RegisterClass来说明其寄存器类型)2.2.2.1. 寄存器2.2.2.1.1. Register今天,可用的目标机器一定有寄存器(完全依靠栈运行...

2017-03-17 11:37:42 3042

原创 llvm学习笔记(2)

2. LLVM的后端描述2.1. 类型描述为了更好地描述寄存器所能支持的值类型(大小),以及操作数的类型(大小),Tablegen在ValueTypes.td里给出了一系列的类型定义,它们都继承自ValueType:16       class ValueType<int size, int value> {17         string Namespace = "...

2017-03-15 11:40:12 2842

翻译 64-ia-32架构优化手册(1)

第二章.Intel®64与IA-32处理器架构本章给出了当前Intel 64与IA-32处理器(基于Intel®微架构Skylate、Intel®微架构Broadwell、Intel®微架构Haswell、Intel®微架构IvyBridge、Intel®微架构SandyBridge的处理器,基于IntelCore微架构、增强IntelCore微架构、Intel®微架构Nehalem的处理器)

2017-03-10 11:21:29 2102

原创 llvm学习笔记(更新1)

1. 概述指令选择(instruction selection,也称为代码选择,有时甚至称为代码生成)是编译器代码生成器后端所涉及的重要问题之一。另外两个重要问题是指令调度与寄存器分配。指令选择器负责通过尽可能地用好可用的机器指令,将程序从目标机器无关的表示翻译到一个目标机器特定的形式。这使得两个正交的子问题必须得到解决:检测何时及何地使用某条机器指令是可能的,并且 在存在多个选项时,决...

2017-03-10 11:15:45 6430 1

Introduction to Theory of Computation

This is a free textbook for an undergraduate course on the Theory of Computation, which we have been teaching at Carleton University since 2002.Until the 2011/2012 academic year, this course was offered as a second-year course (COMP 2805) and was compulsory for all Computer Science students. Starting with the 2012/2013 academic year, the course has been downgraded to a third-year optional course (COMP 3803).

2018-09-23

Survey on Instruction Selection

Instruction selection is one of three optimization problems involved in the code generator back-end of a compiler. The instruction selector is responsible of transforming an input program from its target-independent representation into a target-specific form by making best use of the available machine instructions. Hence instruction selection is a crucial part of efficient code generation.

2018-09-23

Towards a Compilation infrastructure for network processors

Modern network processors (NPs) typically resemble a highly-multithreaded multiprocessor-ona-chip, supporting a wide variety of mechanisms for on-chip storage and inter-task communication. NP applications are themselves composed of many threads that share memory and other resources,and synchronize and communicate frequently. In contrast, studies of new NP architectures and features are often performed by benchmarking a simulation model of the new NP using independent kernel programs that neither communicate nor share memory. In this paper we present a NP simulation infrastructure that (i) uses realistic NP applications that are multithreaded, share memory, synchronize, and communicate; and (ii) automatically maps these applications to a variety of NP architectures and features. We use our infrastructure to evaluate threading and scaling, on-chip storage and communication, and to suggest future techniques for automated compilation for NPs.

2018-09-23

Crafting a Compiler

Brief Contents 1 Introduction 1 2 A Simple Compiler 31 3 Scanning—Theory and Practice 57 4 Grammars and Parsing 113 5 Top-Down Parsing 143 6 Bottom-Up Parsing 179 7 Syntax-Directed Translation 235 8 Symbol Tables and Declaration Processing 279 9 Semantic Analysis 343 10 Intermediate Representations 391 11 Code Generation for a Virtual Machine 417 12 Runtime Support 445 13 Target Code Generation 489 14 Program Optimization 547

2018-09-01

How Debuggers Work

a total guide to debuggers: what they do, how they work, and how to use them to produce better programs

2018-09-01

Compiler Construction-20th

the essays collection of conference of Compiler Construction-20th

2018-09-01

Compiler Construction-19th

the essays collection of conference of Compiler Construction-19th

2018-09-01

Compiler Construction-17th

the essays collection of conference of Compiler Construction-17th

2018-09-01

Compiler Construction-16th

the essays collection of conference of Compiler Construction-16th

2018-09-01

Compiler Construction-5th

the essays collection of conference of Compiler Construction-5th

2018-09-01

Construction and Evolution of Code Generator

It describes the Construction and Evolution of Code Generator

2018-09-01

Compiler Construction-11th

the essays collection of conference Compiler Construction-11th

2018-09-01

The compiler design handbook

The compiler design handbook, which describes the design practice of compiler

2018-09-01

Data_Flow_Analysis_Theory_And_Practice(Bookos.org)

Data Flow Analysis Theory And Practice for compiler development

2018-09-01

The Compiler Design Handbook Optimizations and machine code generation

The Compiler Design Handbook Optimizations and machine code generation

2018-09-01

C++_Coding_Standards_101_Rule

C++ Coding Standards 101 Rule, Andrei Alexandrescu

2018-08-24

instruction scheduling for instruction level parallel processor

instruction scheduling for instruction level parallel processor

2018-07-16

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