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翻译 是时候严肃对待利用未定义行为这件事了

原文地址:http://blog.regehr.org/archives/761作者:John Regehr[注:我答应,暂时来说,这是应该是我最后一篇关于未定义行为的博文。更多后续有来。]当前的C与C++编译器将利用未定义行为来生成高效代码(大量的例子在这里及这里),但不一致或者不好。是时候让我们严肃对待这个问题了。在本文,我将证明利用未定义行为可以显著提升代码速度,同时100%符合

2017-04-28 11:40:35 486

原创 LLVM学习笔记(10)

3.3. 寄存器的后端描述选项“-gen-register-info”会促使Tablegen根据文件TargetRegisterInfo.td中的寄存器定义生成源文件TargetGenRegisterInfo.inc。3.3.1.概述对TD文件中定义的每个寄存器而言,TableGen都会将它们处理为DAG,这些寄存器作为根,它们的子寄存器作为DAG内部节点,其中不包含任何子寄存器的子...

2017-04-28 11:37:33 1921

翻译 更多随机性还是更少

作者:XiWang原文地址:http://kqueue.org/blog/2012/06/25/more-randomness-or-less/CVE-2006-0166是一个将未初始化内存用于随机数生成的名声狼藉的例子。一个Debian维护者注掉了两行代码来使Valgrind闭嘴,它抱怨未初始化内存的使用是熵的一个额外来源,这个改变使得OpenSSL在基于Debian的系统上生成伪键值(

2017-04-20 11:45:21 491

原创 LLVM学习笔记(9)

​​​​​​3.TableGen生成的代码3.1. 概述在编译LLVM时,首先会调用TableGen解析TD文件,产生C++源代码,然后这些C++源代码与LLVM的其他源代码一起被编译为LLVM执行文件。需要解析哪些TD文件是由LLVM/lib/target/target下的Cmakelists.txt文件指定。比如X86机器使用的TD文件有:tablegen(LLVM X86Gen...

2017-04-20 11:39:51 2770

原创 LLVM学习笔记(8)

2.3. 汇编处理描述至于关于读写汇编格式指令信息的封装,TableGen提供了类Target(target.td)作为各目标机器的基类。1059  class Target {1060    // InstructionSet - Instruction set description for this target.1061    InstrInfo InstructionSe...

2017-04-12 11:47:35 2893

翻译 64-ia-32架构优化手册(3)

2.2.5.Haswell-E微架构基于Haswell-E微架构的Intel处理器,如在Haswell微架构中描述的那样,由相同的处理器核组成,但提供更先进的非计算内核与集成I/O功能。基于Haswell-E微架构的处理器支持有多个插槽的平台。Haswell-E微架构支持用于可扩展与高性能的多用途处理器架构及平台配置。由Haswell-E微架构的非计算内核及集成I/O子系统提供的某些功能包

2017-04-07 11:50:32 746

翻译 回顾编译器与停机

作者:John Regehr, Professor of Computer Science, Universityof Utah, USA原文地址:http://blog.regehr.org/archives/161我早先的博文C compilers Disprove Fermat’s Last Theorem在这里及Reddit上产生了大量的讨论。不幸的是,讨论充斥着各种误解。其中一些

2017-04-07 11:47:12 422

原创 LLVM学习笔记(7)

2.2.6. 调度信息在Instruction定义430行的Itinerary以及433行的SchedRW用于描述指令调度的信息。其中Itinerary是从指令执行步骤方面来描述指令。目标机器从InstrItinClass派生对应指令的定义。对像X86这样指令复杂且版本繁多的处理器来说,需要定义的InstrItinClass派生定义数量众多。它们都在X86Schedule.td里,几乎每条...

2017-04-07 11:44:39 2902

Introduction to Theory of Computation

This is a free textbook for an undergraduate course on the Theory of Computation, which we have been teaching at Carleton University since 2002.Until the 2011/2012 academic year, this course was offered as a second-year course (COMP 2805) and was compulsory for all Computer Science students. Starting with the 2012/2013 academic year, the course has been downgraded to a third-year optional course (COMP 3803).

2018-09-23

Survey on Instruction Selection

Instruction selection is one of three optimization problems involved in the code generator back-end of a compiler. The instruction selector is responsible of transforming an input program from its target-independent representation into a target-specific form by making best use of the available machine instructions. Hence instruction selection is a crucial part of efficient code generation.

2018-09-23

Towards a Compilation infrastructure for network processors

Modern network processors (NPs) typically resemble a highly-multithreaded multiprocessor-ona-chip, supporting a wide variety of mechanisms for on-chip storage and inter-task communication. NP applications are themselves composed of many threads that share memory and other resources,and synchronize and communicate frequently. In contrast, studies of new NP architectures and features are often performed by benchmarking a simulation model of the new NP using independent kernel programs that neither communicate nor share memory. In this paper we present a NP simulation infrastructure that (i) uses realistic NP applications that are multithreaded, share memory, synchronize, and communicate; and (ii) automatically maps these applications to a variety of NP architectures and features. We use our infrastructure to evaluate threading and scaling, on-chip storage and communication, and to suggest future techniques for automated compilation for NPs.

2018-09-23

Crafting a Compiler

Brief Contents 1 Introduction 1 2 A Simple Compiler 31 3 Scanning—Theory and Practice 57 4 Grammars and Parsing 113 5 Top-Down Parsing 143 6 Bottom-Up Parsing 179 7 Syntax-Directed Translation 235 8 Symbol Tables and Declaration Processing 279 9 Semantic Analysis 343 10 Intermediate Representations 391 11 Code Generation for a Virtual Machine 417 12 Runtime Support 445 13 Target Code Generation 489 14 Program Optimization 547

2018-09-01

How Debuggers Work

a total guide to debuggers: what they do, how they work, and how to use them to produce better programs

2018-09-01

Compiler Construction-20th

the essays collection of conference of Compiler Construction-20th

2018-09-01

Compiler Construction-19th

the essays collection of conference of Compiler Construction-19th

2018-09-01

Compiler Construction-17th

the essays collection of conference of Compiler Construction-17th

2018-09-01

Compiler Construction-16th

the essays collection of conference of Compiler Construction-16th

2018-09-01

Compiler Construction-5th

the essays collection of conference of Compiler Construction-5th

2018-09-01

Construction and Evolution of Code Generator

It describes the Construction and Evolution of Code Generator

2018-09-01

Compiler Construction-11th

the essays collection of conference Compiler Construction-11th

2018-09-01

The compiler design handbook

The compiler design handbook, which describes the design practice of compiler

2018-09-01

Data_Flow_Analysis_Theory_And_Practice(Bookos.org)

Data Flow Analysis Theory And Practice for compiler development

2018-09-01

The Compiler Design Handbook Optimizations and machine code generation

The Compiler Design Handbook Optimizations and machine code generation

2018-09-01

C++_Coding_Standards_101_Rule

C++ Coding Standards 101 Rule, Andrei Alexandrescu

2018-08-24

instruction scheduling for instruction level parallel processor

instruction scheduling for instruction level parallel processor

2018-07-16

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