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翻译 Intel, AMD及VIA CPU的微架构目录(已完结)

1. 介绍 1.1. 关于本手册 1.2. 本手册涵盖的微处理器版本2. 乱序执行(除了P1、PMMX的所有处理器) 2.1. 指令被分解为微操作 2.2. 寄存器重命名3. 分支预测(所有处理器) 3.1. 条件跳转的预测方法 饱和计数器 带有局部历史表的两层自适应预测器 带有全...

2017-08-18 12:35:59 1329

翻译 64-ia-32架构优化手册(6)

2.4.3.执行核Intel Core微架构的执行核是超标量(superscalar)的,可以乱序处理指令。当一个依赖链导致机器等待一个资源(比如第二级数据缓存行)时,执行核执行其他指令。这增加了每周期被执行指令的总体速率(IPC)。执行核包含以下3个主要部件:·        重命名器(Renamer)——将微操作从前端移到执行核。架构寄存器被重命名器为微架构寄存器。重命名器消除了称

2017-08-25 11:38:45 592

翻译 Intel, AMD及VIA CPU的微架构(2)

2.      乱序执行(除了P1,PMMX的所有处理器)从Ppro开始的第六代Intel微处理器,在微架构实际上,提供了一个重要的,称为乱序执行的改进。思想是,如果由于输入数据尚不可用,一条特定指令的执行被推迟,那么处理器将尝试在后续指令中找出它可以执行的第一条,如果该指令的输入数据已就绪。显然,微处理器必须检查后续指令是否需要前面指令的输出。如果每条指令都依赖之前指令的结果,那么我们没有乱

2017-08-25 11:32:59 810

原创 LLVM学习笔记(17)

3.4.2.4.3. 类型推导3.4.2.4.3.1. 应用类型限定在展开PatFrag模式之后,对展开结果要进行类型推导,采纳其中类型限定的约束,以尽早检查是否有类型错误。这由下面的TreePattern:: InferAllTypes()方法来完成(v7.0的InferAllTypes()版本逻辑上与v3.6.1的是一致的,因此不再列出)。2246 bool TreePatter...

2017-08-25 11:26:37 984

翻译 Intel, AMD及VIA CPU的微架构(1)

Intel, AMD及VIA CPU的微架构对x86平台的优化指引对汇编程序员及编译器作者的优化指引作者:Agner Fog。TechnicalUniversity of Denmark1.      介绍1.1.      关于本手册这是五本手册系列中的第三本:1.      优化C++软件:对Windows,Linux及Mac平台的优化指引。2.      优化

2017-08-18 12:34:18 3500

原创 64-ia-32架构优化手册(5)

2.4. Intel® CORETM微架构与增强的Intel® CORETM微架构Intel Core微架构引入以下特性,使得单线程以及多线程工作负荷都具有高性能与高电源效率:·        Intel® Wide Dynamic Execution使得每个处理器核能够每周期以高带宽获取、分发、执行并回收最多4条指令。这些特性包括:-  14级高效流水线。-  3个算术逻辑单元。

2017-08-18 12:25:48 530

原创 LLVM学习笔记(16)

3.4.2.4. PatFrag的处理3.4.2.4.1. 模式树的构建PatFrag是一个可重用的构件,TableGen会在PatFrag出现的地方展开其定义,有点像C/C++中的宏。为此,CodeGenDAGPatterns将每个可能嵌入PatFrag的定义——Instruction,Pattern,Pat以及PatFrag,构建为一棵TreePattern树,并在适当的时候将其中包含...

2017-08-18 12:05:32 2036

原创 LLVM学习笔记(20)

3.4.3.3.       Match对象序列的优化回到DAGISelEmitter::run。注意PatternMatchers中每个项都是一条Matcher对象链,对应一条指令。在160行生成一个ScopeMatcher对象,把这些项设为自己的孩子。在下面生成的MatcherTable里,它产生的内容将使得SelectCommon方法在匹配一个孩子(即一条指令)失败时,继续进行下一个孩子

2017-08-18 11:49:42 776

翻译 使用LLVM分析函数CFG

作者:Eli Benderskyhttp://eli.thegreenplace.net/2013/09/16/analyzing-function-cfgs-with-llvm在Stack Overflow上,关于LLVM一个常见问题是如何构建一个函数的控制流图(CFG),并对它进行拓扑排序,或者拓扑排序的某些变形。为了节省我将来的回答时间,我认为我应该抛出一篇简明的博文,展示LLVM在

2017-08-11 11:35:11 6433 1

原创 LLVM学习笔记(15)

3.4. DAG指令选择器的生成代码3.4.1. 概述选项-gen-dag-isel用于产生DAG指令选择器,处理这个选项的入口在EmitDAGISel()。TableGen首先根据对指令的描述,为指令定义中的匹配模板(亦称源模板,它指出长怎么样的IR代码片段能匹配这条指令)以及结果模板(它指出匹配成功后指令应该输出怎样的结果,这个结果包含隐含的寄存器的变化)构建DAG实例(下文的展开的T...

2017-08-04 11:39:09 2143

Introduction to Theory of Computation

This is a free textbook for an undergraduate course on the Theory of Computation, which we have been teaching at Carleton University since 2002.Until the 2011/2012 academic year, this course was offered as a second-year course (COMP 2805) and was compulsory for all Computer Science students. Starting with the 2012/2013 academic year, the course has been downgraded to a third-year optional course (COMP 3803).

2018-09-23

Survey on Instruction Selection

Instruction selection is one of three optimization problems involved in the code generator back-end of a compiler. The instruction selector is responsible of transforming an input program from its target-independent representation into a target-specific form by making best use of the available machine instructions. Hence instruction selection is a crucial part of efficient code generation.

2018-09-23

Towards a Compilation infrastructure for network processors

Modern network processors (NPs) typically resemble a highly-multithreaded multiprocessor-ona-chip, supporting a wide variety of mechanisms for on-chip storage and inter-task communication. NP applications are themselves composed of many threads that share memory and other resources,and synchronize and communicate frequently. In contrast, studies of new NP architectures and features are often performed by benchmarking a simulation model of the new NP using independent kernel programs that neither communicate nor share memory. In this paper we present a NP simulation infrastructure that (i) uses realistic NP applications that are multithreaded, share memory, synchronize, and communicate; and (ii) automatically maps these applications to a variety of NP architectures and features. We use our infrastructure to evaluate threading and scaling, on-chip storage and communication, and to suggest future techniques for automated compilation for NPs.

2018-09-23

Crafting a Compiler

Brief Contents 1 Introduction 1 2 A Simple Compiler 31 3 Scanning—Theory and Practice 57 4 Grammars and Parsing 113 5 Top-Down Parsing 143 6 Bottom-Up Parsing 179 7 Syntax-Directed Translation 235 8 Symbol Tables and Declaration Processing 279 9 Semantic Analysis 343 10 Intermediate Representations 391 11 Code Generation for a Virtual Machine 417 12 Runtime Support 445 13 Target Code Generation 489 14 Program Optimization 547

2018-09-01

How Debuggers Work

a total guide to debuggers: what they do, how they work, and how to use them to produce better programs

2018-09-01

Compiler Construction-20th

the essays collection of conference of Compiler Construction-20th

2018-09-01

Compiler Construction-19th

the essays collection of conference of Compiler Construction-19th

2018-09-01

Compiler Construction-17th

the essays collection of conference of Compiler Construction-17th

2018-09-01

Compiler Construction-16th

the essays collection of conference of Compiler Construction-16th

2018-09-01

Compiler Construction-5th

the essays collection of conference of Compiler Construction-5th

2018-09-01

Construction and Evolution of Code Generator

It describes the Construction and Evolution of Code Generator

2018-09-01

Compiler Construction-11th

the essays collection of conference Compiler Construction-11th

2018-09-01

The compiler design handbook

The compiler design handbook, which describes the design practice of compiler

2018-09-01

Data_Flow_Analysis_Theory_And_Practice(Bookos.org)

Data Flow Analysis Theory And Practice for compiler development

2018-09-01

The Compiler Design Handbook Optimizations and machine code generation

The Compiler Design Handbook Optimizations and machine code generation

2018-09-01

C++_Coding_Standards_101_Rule

C++ Coding Standards 101 Rule, Andrei Alexandrescu

2018-08-24

instruction scheduling for instruction level parallel processor

instruction scheduling for instruction level parallel processor

2018-07-16

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