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翻译 64-ia-32架构优化手册(16)

3.4.2.4. 优化循环流检测器(LSD)在Intel Core微架构中,满足以下准则的循环由LSD检测,并从指令队列重播(replay)来供给解码器。必须不超过4个16字节的取指。 必须不超过18条指令。 可以包含不超过4被采用的分支,并且它们不能是RET。 通常应该具有超过64个迭代。在Intel微架构Nehalem中,这样改进循环流寄存器:在指令已解码队列(IDQ,参考...

2018-08-24 11:44:03 416

原创 LLVM学习笔记(40)

3.6. 描述目标机器的数据结构描述目标机器的数据结构由TableGen的“-gen-subtarget”选项生成。以X86来说,生成文件是X86GenSubtargetInfo.Inc。3.6.1. 对目标机器描述的解析这个选项的处理入口是下面的方法:1154 void EmitSubtarget(RecordKeeper &RK, raw_ostream &O...

2018-08-24 11:35:50 639

翻译 Intel, AMD及VIA CPU的微架构(20)

7. Pentium M流水线7.1. PM中的流水线本章适用于Intel Pentium M,Core Solo及Core Duo,但不适用于Core 2。在本手册中缩写PM包括Pentium M,Core Solo与Core Duo。PM构建在与PPro,P2及P3相同的基本微架构上,而P4/NetBurst设计已被中断。在流水线中的主要阶段有:分支预测,指令获取,指令解码,寄存器...

2018-08-17 12:15:13 675

原创 LLVM学习笔记(39)

3.5.2.3.指令描述数组这部分代码输出指令描述数组。首先看到385行的getInstructionsByEnumValue(),指令的这个遍历次序很重要。接着,我们看到387行的SequenceToOffsetTable类型的变量InstrNames,这意味着我们将要进行差分编码。391行则告诉我们,要进行差分编码的是指令的名字。InstrInfoEmitter::run(续)3...

2018-08-17 12:10:54 768

翻译 Intel, AMD及VIA CPU的微架构(19)

6.8. 部分寄存器暂停部分寄存器暂停发生在我们写入一个32位寄存器部分,随后读整个寄存器或更大的部分时。例如:mov al, byte ptr [mem8]mov ebx, eax ; Partial register stall 这给出了5-6个时钟周期的时延。原因是临时寄存器已经被分配给AL,使它与AH无关。执行单元必须等待,直到对AL的写被回收,才可能将AL的值合并到E...

2018-08-10 11:35:12 452

原创 LLVM学习笔记(38)

3.5.2.代码生成这部分代码输出到文件X86GenInstrInfo.inc中。​​​​​​​3.5.2.1.枚举常量从InstrInfoEmitter的构造函数返回到EmitInstrInfo(),接下来调用的InstrInfoEmitter::run()方法来输出相关的代码。342 void InstrInfoEmitter::run(raw_ostream &a...

2018-08-10 11:28:57 770

翻译 64-ia-32架构优化手册(15)

3.4.2. 取指与解码优化Intel Core微架构提供了几个机制来增加前端吞吐量。利用这些特性的技术在下面讨论。3.4.2.1. 对微融合的优化工作在一个寄存器及一个内存操作数上的一条指令解码得到的微操作比对应寄存器-寄存器版本要多。使用寄存器-寄存器版本替换前者指令等效的工作通常要求一个2条指令的序列。这个序列很可能导致取指带宽的降低。Assembly/Compiler编程规...

2018-08-03 11:27:19 367

原创 LLVM学习笔记(37)

3.5.1.7.2. 从InstRW定义推导InstRW为一组指令重新绑定SchedReadWrite。在前面CodeGenSchedModels的createInstRWClass()方法里已经为InstRW定义准备了CodeGenSchedClass对象,并在CodeGenSchedClass对象的InstRWs容器里记录了该InstRW定义的Record实例。但对InstRW定义的处理并...

2018-08-03 11:21:31 623

Introduction to Theory of Computation

This is a free textbook for an undergraduate course on the Theory of Computation, which we have been teaching at Carleton University since 2002.Until the 2011/2012 academic year, this course was offered as a second-year course (COMP 2805) and was compulsory for all Computer Science students. Starting with the 2012/2013 academic year, the course has been downgraded to a third-year optional course (COMP 3803).

2018-09-23

Survey on Instruction Selection

Instruction selection is one of three optimization problems involved in the code generator back-end of a compiler. The instruction selector is responsible of transforming an input program from its target-independent representation into a target-specific form by making best use of the available machine instructions. Hence instruction selection is a crucial part of efficient code generation.

2018-09-23

Towards a Compilation infrastructure for network processors

Modern network processors (NPs) typically resemble a highly-multithreaded multiprocessor-ona-chip, supporting a wide variety of mechanisms for on-chip storage and inter-task communication. NP applications are themselves composed of many threads that share memory and other resources,and synchronize and communicate frequently. In contrast, studies of new NP architectures and features are often performed by benchmarking a simulation model of the new NP using independent kernel programs that neither communicate nor share memory. In this paper we present a NP simulation infrastructure that (i) uses realistic NP applications that are multithreaded, share memory, synchronize, and communicate; and (ii) automatically maps these applications to a variety of NP architectures and features. We use our infrastructure to evaluate threading and scaling, on-chip storage and communication, and to suggest future techniques for automated compilation for NPs.

2018-09-23

Crafting a Compiler

Brief Contents 1 Introduction 1 2 A Simple Compiler 31 3 Scanning—Theory and Practice 57 4 Grammars and Parsing 113 5 Top-Down Parsing 143 6 Bottom-Up Parsing 179 7 Syntax-Directed Translation 235 8 Symbol Tables and Declaration Processing 279 9 Semantic Analysis 343 10 Intermediate Representations 391 11 Code Generation for a Virtual Machine 417 12 Runtime Support 445 13 Target Code Generation 489 14 Program Optimization 547

2018-09-01

How Debuggers Work

a total guide to debuggers: what they do, how they work, and how to use them to produce better programs

2018-09-01

Compiler Construction-20th

the essays collection of conference of Compiler Construction-20th

2018-09-01

Compiler Construction-19th

the essays collection of conference of Compiler Construction-19th

2018-09-01

Compiler Construction-17th

the essays collection of conference of Compiler Construction-17th

2018-09-01

Compiler Construction-16th

the essays collection of conference of Compiler Construction-16th

2018-09-01

Compiler Construction-5th

the essays collection of conference of Compiler Construction-5th

2018-09-01

Construction and Evolution of Code Generator

It describes the Construction and Evolution of Code Generator

2018-09-01

Compiler Construction-11th

the essays collection of conference Compiler Construction-11th

2018-09-01

The compiler design handbook

The compiler design handbook, which describes the design practice of compiler

2018-09-01

Data_Flow_Analysis_Theory_And_Practice(Bookos.org)

Data Flow Analysis Theory And Practice for compiler development

2018-09-01

The Compiler Design Handbook Optimizations and machine code generation

The Compiler Design Handbook Optimizations and machine code generation

2018-09-01

C++_Coding_Standards_101_Rule

C++ Coding Standards 101 Rule, Andrei Alexandrescu

2018-08-24

instruction scheduling for instruction level parallel processor

instruction scheduling for instruction level parallel processor

2018-07-16

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