WinCE6.0 Eboot StartUp.s解析

Eboot中的StartUp.s文件主要完成3个主要任务：SOC初始化、复制自身到RAM、设置页表并启用MMU

具体代码如下：

 INCLUDE kxarm.h          ;符号的宏定义，以便让我们的代码更简单，如宏定义了TEXTAREA、LEAF_ENTRY
 INCLUDE armmacros.s  ;符号的宏定义
 INCLUDE s3c2440a.inc ;定义2440寄存器设置值

;-------------------------------------------------------------------------------

MemoryMap       EQU     0x2a4               ; 676
BANK_SIZE       EQU     0x00100000      ; 1MB per bank in MemoryMap array
BANK_SHIFT      EQU     20

;   Define RAM space for the Page Tables:
PHYBASE         EQU     0x30000000      ; physical start
PTs                   EQU     0x30010000      ; 第一级页表地址(PHYBASE + 0x10000)
                                                                ; save room for interrupt vectors.

;-------------------------------------------------------------------------------

 TEXTAREA

 IMPORT  main

; Set up the MMU and Dcache for bootloader.
;
; This routine will initialize the first-level page table based up the contents
; of the MemoryMap array and enable the MMU and caches.
;初始化第一级页表基于MemoryMap的内容，并使能MMU和caches
; Copy the image to RAM if it's not already running there.
;如果代码不在RAM，拷贝到RAM里运行

 

;------------------------------------------------------------------------------
; Cache Configuration

DCACHE_LINES_PER_SET_BITS   EQU     (6)
DCACHE_LINES_PER_SET             EQU     (64)
DCACHE_NUM_SETS                     EQU     (8)
DCACHE_SET_INDEX_BIT              EQU     (32 - DCACHE_LINES_PER_SET_BITS)
DCACHE_LINE_SIZE                        EQU     (32)

; Pre-defined constants.
;
USERMODE    EQU  0x10
FIQMODE        EQU  0x11
IRQMODE        EQU  0x12
SVCMODE       EQU  0x13
ABORTMODE   EQU  0x17
UNDEFMODE   EQU  0x1b
MODEMASK    EQU  0x1f
NOINT             EQU  0xc0

; Stack locations.
;
SVCStack EQU (_STACK_BASEADDRESS-0x2800)  ; 0x30030000 - 0x2800 ~
UserStack EQU (_STACK_BASEADDRESS-0x3800)     ; 0x30030000 - 0x3800 ~
UndefStack EQU (_STACK_BASEADDRESS-0x2400)  ; 0x30030000 - 0x2400 ~
AbortStack EQU (_STACK_BASEADDRESS-0x2000)  ; 0x30030000 - 0x2000 ~
IRQStack EQU (_STACK_BASEADDRESS-0x1000)     ; 0x30030000 - 0x1000 ~
FIQStack EQU (_STACK_BASEADDRESS-0x0)     ; 0x30030000 - 0x0 ~

;---------------------------------------------------------------------------
; 4 LED light function
; The LEDs are located below AMD Flash ROM

 MACRO
 LED_ON $data
 LDR     r10, =GPFDAT       
 LDR     r11, =$data
 MOV     r11, r11, lsl #4
 STR     r11, [r10]
  MEND
;---------------------------------------------------------------------------

;---------------------------------------------------------------------------
; Voltage Change function
; The LEDs are located below AMD Flash ROM

 MACRO
 VOLTAGECHANGE

 ldr r8, = GPBDAT  ; D4
 ldr r9, [r8]
 ldr r10, = 0x77f
 and r9, r9, r10
 ldr r10, = (D4VAL<<7)
 orr r9, r9, r10
 str r9, [r8]

 ldr r8, = GPFDAT  ; D3~0
 ldr r9, [r8]
 ldr r10, = 0x0f
 and r9, r9, r10
 ldr r10, = ((D3VAL<<7)+(D2VAL<<6)+(D1VAL<<5)+(D0VAL<<4))
 orr r9, r9, r10
 str r9, [r8]

 ldr r8, = GPBCON  ; GPB7: Output
 ldr r9, [r8]
 ldr r10, = 0x3f3fff
 and r9, r9, r10
 ldr r10, = (1<<14)
 orr r9, r9, r10
 str r9, [r8]

 ldr r8, = GPFCON  ; GPF4~7: Output
 ldr r9, [r8]
 ldr r10, = 0x00ff
 and r9, r9, r10
 ldr r10, = 0x5500
 orr r9, r9, r10
 str r9, [r8]

 ldr r8, = GPBDAT  ; Latch enable
 ldr r9, [r8]
 ldr r10, = ~(0<<8)
 and r9, r9, r10
 str r9, [r8]

 ldr r8, = GPBCON  ; GPB8: Output
 ldr r9, [r8]
 ldr r10, = 0x3cffff
 and r9, r9, r10
 ldr r10, = (1<<16)
 orr r9, r9, r10
 str r9, [r8]

 ldr r8, = GPBDAT  ; Output enable
 ldr r9, [r8]
 ldr r10, = (1<<10)
 orr r9, r9, r10
 str r9, [r8]

 ldr r8, = GPBCON  ; GPB10: Output
 ldr r9, [r8]
 ldr r10, = 0x0fffff
 and r9, r9, r10
 ldr r10, = (1<<20)
 orr r9, r9, r10
 str r9, [r8]

 ldr r8, = GPBDAT  ; Latch disable
 ldr r9, [r8]
 ldr r10, = (1<<8)
 orr r9, r9, r10
 str r9, [r8]
 
    MEND
;---------------------------------------------------------------------------

 

;-------------------------------------------------------------------------------
;   Function: Startup
;
;   Main entry point for CPU initialization.
;

        STARTUPTEXT
        LEAF_ENTRY      StartUp
   
        b       ResetHandler

ResetHandler
    VOLTAGECHANGE
   
   ; Make sure that TLB & cache are consistent
    mov     r0, #0
    mcr     p15, 0, r0, c8, c7, 0           ; flush both TLB
    mcr     p15, 0, r0, c7, c5, 0           ; invalidate instruction cache
    mcr     p15, 0, r0, c7, c6, 0           ; invalidate data cache
       
    ldr     r0, = GPFCON
    ldr     r1, = 0x55aa     
    str     r1, [r0]

    ldr     r0, = WTCON                     ; disable watch dog
    ldr     r1, = 0x0        
    str     r1, [r0]

    ldr     r0, = INTMSK
    ldr     r1, = 0xffffffff                     ; disable all interrupts
    str     r1, [r0]

    ldr     r0, = INTSUBMSK
    ldr     r1, = 0x7fff                     ; disable all sub interrupt
    str     r1, [r0]

    ldr     r0, = INTMOD
    mov     r1, #0x0                        ; set all interrupt as IRQ
    str     r1, [r0]

 ldr     r0, = CLKDIVN
 ldr     r1, = CLKDIVVAL               ;MPLL Clock Divider=1:3:6/1:4:8
 str     r1, [r0]

   ; Make AsyncBusMode
 mrc  p15, 0, r0, c1, c0, 0
 orr  r0, r0, #R1_nF:OR:R1_iA
 mcr  p15, 0, r0, c1, c0, 0

 ldr  r0, = LOCKTIME                     ; To reduce PLL lock time, adjust the LOCKTIME register.
 ldr  r1, = 0xffffff
 str  r1, [r0]
 
 ldr     r0, = UPLLCON                  ; Fin=16.9344MHz, UPLL=48/96MHz
 ldr     r1, = UPLLVAL
 str     r1, [r0]

    nop               ; Caution: After UPLL setting, at least 7-clocks delay must be inserted for setting hardware be completed.
    nop
    nop
    nop
    nop
    nop
    nop

 ldr  r0, = CAMDIVN
 ldr  r1, = 0
 str  r1, [r0]

 ldr  r0, = MPLLCON  ; Configure MPLL  ; ;Fin=16.9344MHz, MPLL= 300/399MHz
 ldr     r1, = PLLVAL
 str  r1, [r0]

 mov     r0, #0x200  ; delay
5   subs    r0, r0, #1
    bne     %B5

;------------------------------------------------------------------------------
;   Initialize memory controller

    add     r0, pc, #MEMCTRLTAB - (. + 8)
    ldr     r1, = BWSCON                    ; BWSCON Address
    add     r2, r0, #52                         ; End address of MEMCTRLTAB
40  ldr     r3, [r0], #4   
    str     r3, [r1], #4   
    cmp     r2, r0     
    bne     %B40
   
;------------------------------------------------------------------------------
;   Add for Power Management

    ldr     r1, =GSTATUS2                   ; Determine Booting Mode
    ldr     r10, [r1]

;------------------------------------------------------------------------------
;   Add for Power Management

    tst     r10, #0x2
    beq     BringUpWinCE                    ; Normal Mode Booting

BringUpWinCE

;------------------------------------------------------------------------------
;   Copy boot loader to memory

    ands    r9, pc, #0xFF000000     ; see if we are in flash or in ram
    bne     %f20                              ; go ahead if we are already in ram

    ; This is the loop that perform copying.
    ldr     r0, = 0x38000                  ; offset into the RAM 该RAM偏移值在Eboot.BIB中定义
    add     r0, r0, #PHYBASE          ; add physical base
    mov     r1, r0                             ; (r1) copy destination
    ldr     r2, =0x0                           ; (r2) flash started at physical address 0
    ldr     r3, =0x10000                   ; counter (0x40000/4) 拷贝256K字节
10  ldr     r4, [r2], #4
    str     r4, [r1], #4
    subs    r3, r3, #1
    bne     %b10

    ; Restart from the RAM position after copying.拷贝完毕后从RAM中startup.s起始位置从新执行一遍上面的程序。
    mov pc, r0
    nop
    nop
    nop

    ; Shouldn't get here.
    b  .

    INCLUDE oemaddrtab_cfg.inc                 该文件定义虚拟地址和物理地址的映射关系，很重要。
 

    ; Compute physical address of the OEMAddressTable.
20  add     r11, pc, #g_oalAddressTable - (. + 8)
    ldr     r10, =PTs                ; (r10) = 1st level page table
 
    ; Setup 1st level page table (using section descriptor)    
    ; Fill in first level page table entries to create "un-mapped" regions
    ; from the contents of the MemoryMap array.
    ;
    ;   (r10) = 1st level page table
    ;   (r11) = ptr to MemoryMap array

    add     r10, r10, #0x2000       ; (r10) = ptr to 1st PTE for "unmapped space"
    mov     r0, #0x0E                   ; (r0) = PTE for 0: 1MB cachable bufferable
    orr     r0, r0, #0x400              ; set kernel r/w permission
25  mov     r1, r11                      ; (r1) = ptr to MemoryMap array

       
30  ldr     r2, [r1], #4                  ; (r2) = virtual address to map Bank at
    ldr     r3, [r1], #4                    ; (r3) = physical address to map from
    ldr     r4, [r1], #4                    ; (r4) = num MB to map

    cmp     r4, #0                         ; End of table?
    beq     %f40

    ldr     r5, =0x1FF00000
    and     r2, r2, r5                     ; VA needs 512MB, 1MB aligned.               

    ldr     r5, =0xFFF00000
    and     r3, r3, r5                     ; PA needs 4GB, 1MB aligned.

    add     r2, r10, r2, LSR #18
    add     r0, r0, r3                     ; (r0) = PTE for next physical page

35  str     r0, [r2], #4
    add     r0, r0, #0x00100000   ; (r0) = PTE for next physical page
    sub     r4, r4, #1                     ; Decrement number of MB left
    cmp     r4, #0
    bne     %b35                          ; Map next MB
    bic     r0, r0, #0xF0000000     ; Clear Section Base Address Field
    bic     r0, r0, #0x0FF00000     ; Clear Section Base Address Field
    b       %b30                             ; Get next element
       
40  tst     r0, #8
    bic     r0, r0, #0x0C                ; clear cachable & bufferable bits in PTE
    add     r10, r10, #0x0800       ; (r10) = ptr to 1st PTE for "unmapped uncached space"
    bne     %b25                          ; go setup PTEs for uncached space
    sub     r10, r10, #0x3000       ; (r10) = restore address of 1st level page table

                                                  ; Setup mmu to map (VA == 0) to (PA == 0x30000000).
    ldr     r0, =PTs                       ; PTE entry for VA = 0
    ldr     r1, =0x3000040E          ; uncache/unbuffer/rw, PA base == 0x30000000
    str     r1, [r0]
    ; uncached area.
    add     r0, r0, #0x0800         ; PTE entry for VA = 0x0200.0000 , uncached    
    ldr     r1, =0x30000402         ; uncache/unbuffer/rw, base == 0x30000000
    str     r1, [r0]
      
    ; Comment:
    ; The following loop is to direct map RAM VA == PA. i.e.
    ;   VA == 0x30XXXXXX => PA == 0x30XXXXXX for S3C2442
    ; Fill in 8 entries to have a direct mapping for DRAM
   
    ldr     r10, =PTs               ; restore address of 1st level page table
    ldr     r0,  =PHYBASE

    add     r10, r10, #(0x3000 / 4) ; (r10) = ptr to 1st PTE for 0x30000000

    add     r0, r0, #0x1E               ; 1MB cachable bufferable
    orr     r0, r0, #0x400               ; set kernel r/w permission
    mov     r1, #0
    mov     r3, #64
45  mov     r2, r1                        ; (r2) = virtual address to map Bank at
    cmp     r2, #0x20000000       :SHR:BANK_SHIFT
    add     r2, r10, r2, LSL #BANK_SHIFT-18
    strlo   r0, [r2]
    add     r0, r0, #0x00100000     ; (r0) = PTE for next physical page
    subs    r3, r3, #1
    add     r1, r1, #1
    bgt     %b45

    ldr     r10, =PTs                       ; (r10) = restore address of 1st level page table

    ; The page tables and exception vectors are setup.
    ; Initialize the MMU and turn it on.
    mov     r1, #1
    mcr     p15, 0, r1, c3, c0, 0      ; setup access to domain 0
    mcr     p15, 0, r10, c2, c0, 0

    mcr     p15, 0, r0, c8, c7, 0     ; flush I+D TLBs
    mrc     p15, 0, r1, c1, c0, 0
    and     r1, r1, #0xC0000000      ; [31:30] AsyncBusMode Enable, [12] ICache Disable(UMON set enable)
    orr     r1, r1, #0x0079                ; [0] Enable MMU, [6:3] Reserved 1111
    orr     r1, r1, #0x4000                ; Round-Robind Cache Replacement Policy
    orr     r1, r1, #0x1000                ; Enable ICache (with MMU On)
    orr     r1, r1, #0x0004                ; Enable the Dcache, (with MMU On)

    ldr     r0, =VirtualStart

    cmp     r0, #0                             ; make sure no stall on "mov pc,r0" below
    mcr     p15, 0, r1, c1, c0, 0
    mov     pc, r0                             ;  & jump to new virtual address
    nop

     ; MMU & caches now enabled.
     ;   (r10) = physcial address of 1st level page table
     ;

VirtualStart

    mov     sp, #0x80000000
    add     sp, sp, #0x30000        ; arbitrary initial super-page stack pointer

    ; Stack Setup for C
 mrs r0, cpsr
 bic r0, r0, #MODEMASK|NOINT
 orr r1, r0, #IRQMODE
 msr cpsr_cxsf, r1    ; IRQMode.
 ldr sp, =IRQStack

 mrs r0, cpsr
 bic r0, r0, #MODEMASK|NOINT
 orr r1, r0, #SVCMODE
 msr cpsr_cxsf, r1    ; SVCMode.
 ldr sp, =SVCStack

    b       main

    

led_loop

 ldr  r0, =GPFCON
 ldr r1, =0x55aa
 str  r1, [r0]

 ldr  r0, =GPFDAT
 ldr r1, =0xF0
 str  r1, [r0]
 
 ldr r0, =0x2000000
10 subs  r0, r0, #1
 bne %B10
 
 ldr  r0, =GPFDAT
 ldr r1, =0xC0
 str  r1, [r0]

 ldr r0, =0x2000000
20 subs  r0, r0, #1
 bne %B20

 b led_loop
 
        LTORG

;------------------------------------------------------------------------------
;   Memory Controller Configuration Data Table
;
;   This data block is loaded into the memory controller's
;   registers to configure the platform memory.
;

MEMCTRLTAB DATA
        DCD (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28))
        DCD ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC))   ; BANKCON0
        DCD ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC))   ; BANKCON1
        DCD ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC))   ; BANKCON2
        DCD ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC))   ; BANKCON3
        DCD ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC))   ; BANKCON4
        DCD ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC))   ; BANKCON5
        DCD ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN))                                                        ; BANKCON6
        DCD ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN))                                                        ; BANKCON7
        DCD ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT)                            ; REFRESH
        DCD (0xB0|BK76MAP)                                                                              ; BANKSIZE
        DCD 0x30                                                                                        ; MRSRB6
        DCD 0x30                                                                                        ; MRSRB7

        END

 

 

转自：http://cdj-811.blog.163.com/blog/static/41723257201051110928315/