Introduction to Verilog （Verilog 简介）

Introduction to Verilog  //Verilog简介

Introduction        //简介

Bottom-Up Design //自底向上设计

Top-Down Design //自顶向下设计

Figure shows a Top-Down design approach.   自定向下设计流图

Design Styles    //设计风格

Behavioral level     //行为级 Register-Transfer Level //RTL级（寄存器传输级）   Gate Level                     //门级

the above original link:http://www.asic-world.com/verilog/intro.html

  Introduction

		Introduction       //简介
		Verilog is a HARDWARE DESCRIPTION LANGUAGE (HDL). A hardware description language is a language used to describe a digital system: for example, a network switch, a microprocessor or a memory or a simple flip-flop. This just means that, by using a HDL, one can describe any (digital) hardware at any level. Verilog HDL是一种硬件描述语言（Verilog HDL, Hardware Description Language, 其实Verilog 是另外一种语言叫 verify logical). 一种硬件描述语言使用一种用来描述数字系统的语言。这种数字系统有网络交换机（network switch），微处理器，存储器，以及简单触发器。这也意味着，人们可以使用HDL从任何级别描述一个数字硬件系统。
		//D触发器即Vreilog HDL描述
		1 // D flip-flop Code 2 module d_ff ( d, clk, q, q_bar); 3 input d ,clk; 4 output q, q_bar; 5 wire d ,clk; 6 reg q, q_bar; 7 8 always @ (posedge clk) 9 begin 10 q <= d; 11 q_bar <= ! d; 12 end 13 14 endmodule You could download file d_ff.v here  //点击download D触发器的源码
		One can describe a simple Flip flop as that in the above figure, as well as a complicated design having 1 million gates. Verilog is one of the HDL languages available in the industry for hardware designing. It allows us to design a Digital design at Behavior Level, Register Transfer Level (RTL), Gate level and at switch level. Verilog allows hardware designers to express their designs with behavioral constructs, deferring the details of implementation to a later stage in the final design. 人们可以描述一个如上图中简单触发器，同样也可以描述一个具有1百万门的复杂器件的设计。Verilog HDL 是一种工业级可用的硬件描述语言。它可以使开发人员进行行为级、寄存器传输级（RTL）门级、甚至开关级的设计。Verilog HDL可以使硬件设计者从行为级构建设计，从而可以推迟硬件的具体实现，到最终设计的下一阶段。
		Many engineers who want to learn this language, very often ask this question, how much time will it take to learn Verilog? Well my answer to them is "It may take no more than one week, if you happen to know at least one programming language". 许多想学习Verilog HDL语言的工程师总会提出这样的问题：我要花多久的时间学习Verilog HDL？然而我告诉他们如果你至少了解一门编程语言的话，他将花不了你一周的时间。
		Design Styles  //设计风格
		Verilog, like any other hardware description language, permits a design in either Bottom-up or Top-down methodology. 与其他硬件描述语言一样，Verilog允许你使用自底向上或者自顶向下的方法进行设计。
		Bottom-Up Design  //自底向上的设计方法
		The traditional method of electronic design is bottom-up. Each design is performed at the gate-level using the standard gates (refer to the Digital Section for more details). With the increasing complexity of new designs this approach is nearly impossible to maintain. New systems consist of ASIC or microprocessors with a complexity of thousands of transistors. These traditional bottom-up designs have to give way to new structural, hierarchical design methods. Without these new practices it would be impossible to handle the new complexity. 传统的电子设计方法是自底向上。 每个设计都是基于门级的，使用标准的门器件（参考数字系统部分的具体细节）。随着设计的复杂度的提高，这种设计方法变得几乎不可行。由ASIC(Application Specific Integrated Circuit )或者微处理器的新系统将有成千上万个晶体管组成。  这些传统的自底向上的设计方法将让路于新的结构化、层次化的设计方法。如果不使用这些新的设计方法，将无法处理这种新的复杂度。
		Top-Down Design //自顶向下的设计
		The desired design-style of all designers is the top-down one. A real top-down design allows early testing, easy change of different technologies, a structured system design and offers many other advantages. But it is very difficult to follow a pure top-down design. Due to this fact most designs are a mix of both methods, implementing some key elements of both design styles. 所有设计者的期待的设计风格是自顶向下的设计方法。一个真正的自顶向下的设计可以进行早期的测试，方便地在不同的技术间变换，结构化的设计并且提供其他的许多优点。但是，很难实现一个完全的自顶向下的设计。 基于这样一个事实，大多数设计都是这两种方法的一个混合体（复方）， 用这两种方法实现一些关键部分。
		Figure shows a Top-Down design approach.
		//自顶向下的设计方法流图
		需求分析（specification，规范说明）=》上层设计（High Level Design ，高级设计）=》底层设计（low LevelDesign） =》RTL级编码 (RTL Coding)=>功能验证（Fuctional Verification) => 逻辑综合（Logical Synthesis） =>布局、布线（place and route)=>晶圆加工（Fabrication）=》封装测试（post Si Validation）。
		Verilog Abstraction Levels  //Verilog HDL 抽象级
		Verilog supports designing at many different levels of abstraction. Three of them are very important: Verilog HDL 支持不同级别的抽象。 其中的有三种非常重要：
		Behavioral level     //行为级 Register-Transfer Level  //寄存器传输级 （RTL 级） Gate Level                   //门级
		Behavioral level  //行为级建模
		This level describes a system by concurrent algorithms (Behavioral). Each algorithm itself is sequential, that means it consists of a set of instructions that are executed one after the other. Functions, Tasks and Always blocks are the main elements. There is no regard to the structural realization of the design. 这种级别的建模通过并行算法（Behavioral 行为）来描述一个系统。每个算法自身是一个串行的，也就是说它又一些列先后执行的指令集构成。其中Fuctions、Tasks、 Always 代码块是主要成员。这与设计的结构实现没有关系。
		Register-Transfer Level //寄存器传输级
		Designs using the Register-Transfer Level specify the characteristics of a circuit by operations and the transfer of data between the registers. An explicit clock is used. RTL design contains exact timing bounds: operations are scheduled to occur at certain times. Modern RTL code definition is "Any code that is synthesizable is called RTL code". 使用寄存器传输级（RTL级）的设计可以通过操作指派电路特性和寄存器间的数据传输。一个显式的时钟信号被使用。 RTL级的设计有着严格的时间界限：某个操作必须安排在一个给定的时刻发生。 现代的RTL Code的定义是 任何可综合的Code 就称为RTL级的Code。
		Gate Level  //门级
		Within the logic level the characteristics of a system are described by logical links and their timing properties. All signals are discrete signals. They can only have definite logical values (`0', `1', `X', `Z`). The usable operations are predefined logic primitives (AND, OR, NOT etc gates). Using gate level modeling might not be a good idea for any level of logic design. Gate level code is generated by tools like synthesis tools and this netlist is used for gate level simulation and for backend. 在逻辑门级，系统的特性使用逻辑链路和它们的时间属性。所有的信号都是离散信号。 这些信号可以有唯一一个确定的逻辑值 （0， 1， X（未知），Z（高阻））。一些有用的操作是一些预定义的原语（逻辑门 And， or， not 等等）。使用门级建模对于任何逻辑设计都不是一个好的设计。门级的编码一般都是有综合工具产生的，和用于门级的仿真netlist（网表）为后端。

the original link: http://www.asic-world.com/verilog/intro1.html#Introduction