Verilog HDL Syntax And Semantics Part-I

Lexical Conventions //词法约定

The basic lexical conventions used by Verilog HDL are similar to those in the C programming language. 

Verilog HDL is a case-sensitive language. All keywords are in lowercase.

Verilog HDL使用的基本词法约定和C语言中的词法约定相似。 Verilog HDL 是一种大小写敏感的语言。 所有的关键字都是小写。

White Space 空白符

White space can contain the characters for blanks, tabs, newlines, and form feeds. These characters are ignored except when they serve to separate other tokens. However, blanks and tabs are significant in strings. 空白符包括空格符、tab符（制表符）、换行符和格式馈给。它们除了用来分隔标识符情形外，总是被忽略。然而，字符串中空格和tabs（制表符）是有效的。

White space characters are : //空白字符

Blank spaces  //空格符 Tabs              // tab制表符 Carriage returns //回车符 New-line         //换行符 Form-feeds     //格式馈给

		Examples of White Spaces //空白符举例
		Functional Equivalent Code //功能等价代码
		Bad Code : Never write code like this.  //风格不好的代码：永远不要写这样的代码
		1 module addbit(a,b,ci,sum,co); 2 input a,b,ci;output sum co; 3 wire a,b,ci,sum,co;endmodule You could download file bad_code.v here
		Good Code : Nice way to write code.  //风格好的代码： 非常好的书写代码的方法
		1 module addbit ( 2 a, 3 b, 4 ci, 5 sum, 6 co); 7 input a; 8 input b; 9 input ci; 10 output sum; 11 output co; 12 wire a; 13 wire b; 14 wire ci; 15 wire sum; 16 wire co; 17 18 endmodule You could download file good_code.v here
		Comments //注释
		There are two forms to introduce comments. //有2种形式的注释
		Single line comments begin with the token // and end with a carriage return  // 单行注释使用 // Multi line comments begin with the token /* and end with the token */       //多行注释
		Examples of Comments //注释的举例
		1 /* This is a 2 Multi line comment //多行注释 3 example */ 4 module addbit ( 5 a, 6 b, 7 ci, 8 sum, 9 co); 10 11 // Input Ports Single line comment //单行注释 12 input a; 13 input b; 14 input ci; 15 // Output ports // 单行注释 16 output sum; 17 output co; 18 // Data Types //单行注释 19 wire a; 20 wire b; 21 wire ci; 22 wire sum; 23 wire co; 24 25 endmodule You could download file comment.v here
		Case Sensitivity   //大小写敏感
		Verilog HDL is case sensitive    //Verilog HDL 是一种大小写敏感的语言。
		Lower case letters are unique from upper case letters //小写字母和大写字母是不同的 All Verilog keywords are lower case                     //所有的关键字都是小写
		Examples of Unique names //唯一性命名举例
		1 input // a Verilog Keyword //Verilog的关键字 2 wire // a Verilog Keyword // Verilog的关键字 3 WIRE // a unique name ( not a keyword) //一个变量名而不是关键字 4 Wire // a unique name (not a keyword) //变量名而非关键字 You could download file unique_names.v here
		NOTE : Never use Verilog keywords as unique names, even if the case is different. 注意：绝对不要使用Verilog 的关键字作为变量名，即使大小写不同。
		Identifiers // 标识符
		Identifiers are names used to give an object, such as a register or a function or a module, a name so that it can be referenced from other places in a description. 标识符时指定对象的名字，如一个register或者一个function或者一个module。这个名字可以用在描述上下文的其他地方(引用，reference）。
		Identifiers must begin with an alphabetic character or the underscore character (a-z A-Z _ ) 标识符必须以字母字符或者下划线（underscore)作为其开头字符 Identifiers may contain alphabetic characters, numeric characters, the underscore, and the dollar sign (a-z A-Z 0-9 _ $) 标识符中可以包含字母字符、数字字符、下划线、和$。 Identifiers can be up to 1024 characters long. 标识符最长可达1024个字符
		Examples of legal identifiers //合法标识符举例
		data_input mu
		clk_input my$clk
		i386 A

Escaped Identifiers //转义标识符

Verilog HDL allows any character to be used in an identifier by escaping the identifier. Escaped identifiers provide a means of including any of the printable ASCII characters in an identifier (the decimal values 33 through 126, or 21 through 7E in hexadecimal). Verilog HDL允许标识符通过转义使用任何字符。 转义标识符提供了一种可以在标识符中使用任何可打印字符的方法。（可打印字符的ASCII（33-126）。

Escaped identifiers begin with the back slash ( \ )  //转义标识符以\（back slash，反斜杠开头  Entire identifier is escaped by the back slash.   //整个标识符被\（back slash)反斜杠转义。   Escaped identifier is terminated by white space (Characters such as commas, parentheses, and semicolons become part of the escaped identifier unless preceded by a white space) //转义字符使用空白终止（像逗号（comma)、（）括号（parentheses）和分号等字符都是转义标识符一部分，除非有个前导的空白符。 Terminate escaped identifiers with white space, otherwise characters that should follow the identifier are considered as part of it. 用空白符终止转义标识符，否则标识符后面的字符被认为是标识符的一部分。

Examples of escape identifiers //转义标识符举例

Verilog does not allow to identifier to start with a numeric character.  So if you really want to use a identifier to start with a numeric value then use a escape character as shown below. Verilog HDL 不允许标识符以数字字符开头。 如果你真的想使用一个以数字开头的标识符，那么你可以像下面一样使用转义字符。

1 // There must be white space after the 2 // string which uses escape character //转义标识符的后面必须有一个空白符 3 module \1dff ( 4 q, // Q output 5 \q~ , // Q_out output 6 d, // D input 7 cl$k, // CLOCK input 8 \reset* // Reset input 9 ); 10 11 input d, cl$k, \reset* ; 12 output q, \q~ ; 13 14 endmodule You could download file escape_id.v here

Numbers in Verilog

You can specify constant numbers in decimal, hexadecimal, octal, or binary format. Negative numbers are represented in 2's complement form. When used in a number, the question mark (?) character is the Verilog alternative for the z character. The underscore character (_) is legal anywhere in a number except as the first character, where it is ignored. 你可以指派常量数字以十进制（decimal）、十六进制（hexdecimal）、八进制（octal）、或者二进制（binary）的格式。负数使用2的补码表示。数字中的？标志可选的。 数字中的下划线（underscore）只要不出现在开头都是合法的，而且其所在的地方可以忽略。

Integer Numbers //整数数字

Verilog HDL allows integer numbers to be specified as

Verilog HDL 中允许的整数数字可以指派为如下：

Sized or unsized numbers (Unsized size is 32 bits)  //指定位数的，和没有指定位数的（32位） In a radix of binary, octal, decimal, or hexadecimal    //基数可以2， 8， 10， 16 Radix and hex digits (a,b,c,d,e,f) are case insensitive //基数和十六进制的是大小写敏感的 Spaces are allowed between the size, radix and value //空格可以出现在 位数、基数、值之间。
Syntax: <size>'<radix><value>;  语法格式 ： 4`b1100;   //4位二进制数1100；

Example of Integer Numbers //整数举例

Integer Stored as 1 00000000000000000000000000000001 8'hAA 10101010 6'b10_0011 100011 'hF 00000000000000000000000000001111
Verilog expands <value> filling the specified <size> by working from right-to-left Verilogco从右至左扩展<值>填充指定的<size>

When <size> is smaller than <value>, then leftmost bits of <value> are truncated 当<size>小于<value>的位数， <value>最左边的位将被截断。 When <size> is larger than <value>, then leftmost bits are filled, based on the value of the leftmost bit in <value>. 如果当<size>比<value>的位数大的话，最左边的位要以value的最左边的位决定填充， Leftmost '0' or '1' are filled with '0' //0填充 Leftmost 'Z' are filled with 'Z'      //Z填充 Leftmost 'X' are filled with 'X'      //X填充

Note : X Stands for unknown and Z stands for high impedance, 1 for logic high or 1 and 0 for logic low or 0. 注意：X代表未知，Z代表高阻， 1代表逻辑高电平，0代表逻辑低电平。

Example of Integer Numbers

Integer Stored as 6'hCA 001010 6'hA 001010 16'bZ ZZZZZZZZZZZZZZZZ 8'bx xxxxxxxx

Real Numbers //实数

Verilog supports real constants and variables //Verilog支持实数型常量和变量 Verilog converts real numbers to integers by rounding //Verilog通过近似将实数转化为整数 Real Numbers can not contain 'Z' and 'X' //实数中不能包含Z和X Real numbers may be specified in either decimal or scientific notation //实数可以采用十进制活科学计数法 < value >.< value >   //value.value < mantissa >E< exponent > //尾数E指数 Real numbers are rounded off to the nearest integer when assigning to an integer. //实数给整数赋值时，四舍五入到最接近的整数。

Example of Real Numbers //实数举例

Real Number Decimal notation 1.2 1.2 0.6 0.6 3.5E6 3,500000.0

Signed and Unsigned Numbers //有符号数和无符号数

Verilog Supports both types of numbers, but with certain restrictions. Like in C language we don't have int and unint types to say if a number is signed integer or unsigned integer. Verilog同时支持有符号数和无符号两种数据类型，但是有一定的限制。像C语言一样，我们没有设置int 和unint类型来之处一个数字是有符号数还是无符号数。

Any number that does not have negative sign prefix is a positive number. Or indirect way would be "Unsigned".

任何整数没有负号（-）前缀的都认为是正数，或者通过unsigned的关键字指示。

Negative numbers can be specified by putting a minus sign before the size for a constant number, thus they become signed numbers. Verilog internally represents negative numbers in 2's complement format. An optional signed specifier can be added for signed arithmetic. 负数可以通过在将负号（minus -）放在常量的size前面，同样成了一个有符号数。Verilog在内部通过的2的补码表示一个负数。一个可选的负号指派符可以增加到有符号算术中。

Examples

Number	Description
32'hDEAD_BEEF	Unsigned or signed positive number
-14'h1234	Signed negative number

The example file below shows how Verilog treats signed and unsigned numbers.

//下面这个文件展示了Verilog HDL中怎样处理有符号数和无符号数的。

  1 module signed_number;
  2 
  3 reg [31:0]  a;
  4 
  5 initial begin
  6   a = 14'h1234;
  7   $display ("Current Value of a = %h", a);
  8   a = -14'h1234;
  9   $display ("Current Value of a = %h", a);
 10   a = 32'hDEAD_BEEF;
 11   $display ("Current Value of a = %h", a);
 12   a = -32'hDEAD_BEEF;
 13   $display ("Current Value of a = %h", a);
 14    #10  $finish;
 15 end
 16 
 17 endmodule    

You could download file signed_number.v here

Current Value of a = 00001234
 Current Value of a = ffffedcc
 Current Value of a = deadbeef
 Current Value of a = 21524111

http://www.asic-world.com/verilog/syntax1.html