[code=C/C++] static void omap3_disp_config_dispc(int is_rfbi) { u32 dispc_sysc; u32 temp; int wait; struct omap_video_timings timings; DEBUG_INFO("Entering %s/n",__FUNCTION__); /*reset DISPC*/ dispc_reg_out(DISPC_SYSCONFIG,1 << 1); wait = 1 << 28; while(!(dispc_reg_in(DISPC_SYSSTATUS) & 1) && --wait){} if(wait <= 0){DEBUG_INFO("%s:reset dispc error/n",__FUNCTION__);return;} #ifdef LCD_CLOCK_ALWON /*all clocks are always on*/ dispc_sysc= dispc_reg_in(DISPC_SYSCONFIG); dispc_sysc &= ~((3 << 12) | (3 << 3)); dispc_sysc |= (1 << 12) | (1 << 3) | (3 << 8) | (1 << 2); dispc_reg_out(DISPC_SYSCONFIG,dispc_sysc); /*function clock gated disabled*/ temp = dispc_reg_in(DISPC_CONFIG); temp &= ~(1 << 9); dispc_reg_out(DISPC_CONFIG, temp); #else /* Enable smart standby/idle, autoidle and wakeup */ dispc_sysc = dispc_reg_in(DISPC_SYSCONFIG); dispc_sysc &= ~((3 << 12) | (3 << 3)); dispc_sysc |= (2 << 12) | (2 << 3) | (1 << 2) | (1 << 0); dispc_reg_out(DISPC_SYSCONFIG,dispc_sysc); /* Set functional clock autogating */ temp = dispc_reg_in(DISPC_CONFIG); temp |= 1 << 9; dispc_reg_out(DISPC_CONFIG, temp); #endif /*config timings*/ if(!is_rfbi){ timings.x_res = LCD_WIDTH; timings.y_res = LCD_HEIGH; timings.hsw = HSW; timings.hfp = HFP; timings.hbp = HBP; timings.vsw = VSW; timings.vfp = VFP; timings.vbp = VBP; omap3_disp_set_lcd_timings(timings); } /*reset all the status of module internal events*/ dispc_reg_out(DISPC_IRQSTATUS,0x7FFF); /*all interrupts are not masked*/ dispc_reg_out(DISPC_IRQENABLE,0x1ffff); /* Set logic clock to fck, pixel clock to fck/2 for now */ dispc_reg_out(DISPC_DIVISOR, 1 << 16 | 6 << 0); /*VSYNC,HSYNC are low active,data are driven on data lines on falling edge of pixel clock*/ dispc_reg_out(DISPC_POL_FREQ, POL_FREQ_VALUE); /*frame data only loaded every frame*/ temp = 2 << 1; dispc_reg_out(DISPC_CONFIG,temp); temp = dispc_reg_in(DISPC_CONTROL); /* Enable RFBI, GPIO0/1 */ temp &= ~((1 << 11) | (1 << 15) | (1 << 16)); /* Stall mode,RFBI En: GPIO0/1=10 RFBI Dis: GPIO0/1=11,TFT,16 bits*/ if(is_rfbi) temp |= 1 << 11 | 1 << 15 | 1 << 3 | 1 << 8; else temp |= 1 << 15 | 1 << 16 |1 << 3 | 1 << 8; dispc_reg_out(DISPC_CONTROL,temp); omap3_disp_golcd(); DEBUG_INFO("%s exit!/n",__FUNCTION__); } [/code]