spinal scala学习记录

1 counter计数器

DUT 部分
模块1 ： 用于生成verilog代码

package workshop.counter
import spinal.core._

//Run this main to generate the RTL
object CounterMain{
  def main(args: Array[String]) {
      SpinalConfig(targetDirectory = "rtl").generateVerilog(Counter(width = 4))
  }
}

counter 主程序：

package workshop.counter

import spinal.core._

case class Counter(width: Int) extends Component {
  val io = new Bundle {
    val clear    = in  Bool
    val value    = out UInt(width bits)
    val full     = out Bool
  }

  val counter = Reg(UInt(width bits)) init(0)
  counter := counter + 1
  if(io.clear == 1) {
    counter := 0
  }


  io.value := counter
  io.full := counter === U(counter.range->true)

 }

tb部分：

package workshop.counter

import org.scalatest.FunSuite
import spinal.core._
import spinal.core.sim._
import spinal.sim.Suspendable
import workshop.common.WorkshopSimConfig

import scala.sys.process._
import scala.util.Random

//Run this scala test to generate and check that your RTL work correctly
class CounterTester extends FunSuite {
  var compiled: SimCompiled[Counter] = null

  test("compile") {
    compiled = WorkshopSimConfig().compile(Counter(width = 4))
  }

  test("testbench") {
    compiled.doSim{dut =>
      dut.clockDomain.forkStimulus(10)
      var counter = 0
      Suspendable.repeat(100){
        dut.io.clear #= Random.nextDouble() < 0.1
        dut.clockDomain.waitSampling()
        assert(dut.io.value.toInt == counter, "dut.io.value missmatch")
        assert(dut.io.full.toBoolean == (counter == 15), "dut.io.full missmatch")
        counter = if(dut.io.clear.toBoolean) 0 else (counter + 1) & 0xF
      }
    }
  }
}