4412的SPI接口驱动

4412的SPI控制器用两个8，16，32bit移位寄存器来发送和接受数据，全双工full duplex，

Two independent 32-bits wide transmit and receive FIFOs: depth 64 in port 0 and depth 16 in port 1 and 2 

CPU (or DMA) must write data on the register SPI_TX_DATA, to write data in FIFO. Data on the register are
automatically moved to Tx FIFOs. To read data from Rx FIFOs, CPU (or DMA) must access the register 
SPI_RX_DATA and data are automatically sent to the SPI_RX_DATA register. CMU registers can control SPI operating frequency.

SPI has two modes, namely, master and slave mode. In master mode, SPICLK is generated and transmitted to 
external device. XspiCS#, which is the signal to select slave, indicates that the data is valid when XspiCS# is set 
to low level. XspiCS# must be set low before packets are transmitted or received. 

SPI controls the number of packets to be received in master mode. Set SFR (PACKET_CNT_REG) to receive any 
number of packets. SPI stops generating SPICLK if the number of packets is similar to PACKET_CNT_REG.

The size of one packet depends on channel width. (One packet is one byte when you configure channel width as byte, 
and one packet is four bytes when you configure channel width as word.)

 It is mandatory to follow software or hardware reset before reloading this function. (Software reset can clear all registers except special function 
registers, but hardware reset clears all registers.)