[RK3399][Android7.1][Camera]IMX307 mclk 37.125M补丁

参考rk3288 7.1 IMX307 cif clk out 37.125M补丁，移植过来，rk3399还是无法分出37.125M

RK3399默认cif clk默认选择的是GPLL 800M作为母时钟，无法分出37.125M，RK3399默认时钟树里没有594M母时钟

只有选择最接近594M NPLL（NPLL默认600M），驱动代码也需要修改，否则无法设置成37.125M，

cat ./sys/kernel/debug/clk/clk_summary |grep cif
          clk_cifout_src                  0            3   594000000          0 0
                clk_cifout                   0            2    37125000           0 0

完整补丁如下：

diff --git a/kernel/arch/arm64/boot/dts/rockchip/rk3399-d20pro.dts b/kernel/arch/arm64/boot/dts/rockchip/rk3399-d20pro.dts
index eb60280..2481f1d 100755
--- a/kernel/arch/arm64/boot/dts/rockchip/rk3399-d20pro.dts
+++ b/kernel/arch/arm64/boot/dts/rockchip/rk3399-d20pro.dts
@@ -955,10 +955,22 @@
 
 &isp0 {
        status = "okay";
+
+       // start for camera IMX307 mclk "sclk_vip_out" set 37.125M by lpz add
+       assigned-clocks = <&cru PLL_NPLL>, <&cru SCLK_CIF_OUT_SRC>, <&cru SCLK_CIF_OUT>;
+       assigned-clock-parents = <&cru PLL_NPLL>;
+       assigned-clock-rates = <594000000>, <594000000>, <37125000>;
+       // end for camera IMX307 mclk "sclk_vip_out" set 37.125M by lpz add
 };
 
 &isp1 {
        status = "okay";
+
+       // start for camera IMX307 mclk "sclk_vip_out" set 37.125M by lpz add
+       assigned-clocks = <&cru PLL_NPLL>, <&cru SCLK_CIF_OUT_SRC>, <&cru SCLK_CIF_OUT>;
+       assigned-clock-parents = <&cru PLL_NPLL>;
+       assigned-clock-rates = <594000000>, <594000000>, <37125000>;
+       // end for camera IMX307 mclk "sclk_vip_out" set 37.125M by lpz add
 };
 
 &isp0_mmu {
diff --git a/kernel/drivers/media/video/rk_camsys/camsys_cif.c b/kernel/drivers/media/video/rk_camsys/camsys_cif.c
old mode 100644
new mode 100755
index fce0784..a597ea6
--- a/kernel/drivers/media/video/rk_camsys/camsys_cif.c
+++ b/kernel/drivers/media/video/rk_camsys/camsys_cif.c
@@ -148,7 +148,9 @@ static int camsys_cif_clkout_cb(void *ptr, unsigned int on, unsigned int clkin)
        spin_lock(&clk->lock);
        if (on && (clk->out_on != on)) {
                clk_prepare_enable(clk->cif_clk_out);
-               clk_set_rate(clk->cif_clk_out, clkin);
+               //start for camera IMX307 mclk "sclk_vip_out" set 37.125M by lpz add
+               //clk_set_rate(clk->cif_clk_out, clkin);
+               //end for camera IMX307 mclk "sclk_vip_out" set 37.125M by lpz add
 
                clk->out_on = on;
                camsys_trace(1,  "%s clock out(rate: %dHz) turn on",
diff --git a/kernel/drivers/media/video/rk_camsys/camsys_marvin.c b/kernel/drivers/media/video/rk_camsys/camsys_marvin.c
old mode 100644
new mode 100755
index 0f849a8..1a713ff
--- a/kernel/drivers/media/video/rk_camsys/camsys_marvin.c
+++ b/kernel/drivers/media/video/rk_camsys/camsys_marvin.c
@@ -566,6 +566,7 @@ static int camsys_mrv_clkin_cb(void *ptr, unsigned int on)
                                clk_prepare_enable(clk->pclk_dphytxrx);
 
                                clk_prepare_enable(clk->pclkin_isp);
+                               clk_prepare_enable(clk->cif_clk_out);
                        } else {
                                clk_set_rate(clk->clk_isp0, isp_clk);
                                clk_prepare_enable(clk->hclk_isp0_noc);
@@ -682,7 +683,9 @@ static int camsys_mrv_clkout_cb(void *ptr, unsigned int on, unsigned int inclk)
 
        mutex_lock(&clk->lock);
        if (on && (clk->out_on != on)) {
-               clk_set_rate(clk->cif_clk_out, inclk);
+               //start for camera IMX307 mclk "sclk_vip_out" set 37.125M by lpz add
+               //clk_set_rate(clk->cif_clk_out, inclk);
+               //end for camera IMX307 mclk "sclk_vip_out" set 37.125M by lpz add
                clk_prepare_enable(clk->cif_clk_out);
                clk->out_on = on;
                camsys_trace(1, "%s clock out(rate: %dHz) turn on",
@@ -691,7 +694,9 @@ static int camsys_mrv_clkout_cb(void *ptr, unsigned int on, unsigned int inclk)
        } else if (!on && clk->out_on) {
                if (!IS_ERR_OR_NULL(clk->cif_clk_pll)) {
                        /* just for closing clk which base on XIN24M */
-                       clk_set_rate(clk->cif_clk_out, 36000000);
+                       //clk_set_rate(clk->cif_clk_out, 36000000);
+                       clk_set_parent(clk->cif_clk_out,
+                               clk->cif_clk_pll);
                } else {
                        camsys_warn("%s clock out may be not off!",
                                dev_name(camsys_dev->miscdev.this_device));
(END)