杭电计算机组成实验8，9，10实现RIUSJB型指令的CPU设计实验

yangjiaer

已于 2023-07-09 11:14:19 修改

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文章标签：嵌入式硬件

于 2023-07-07 17:18:41 首次发布

本文链接：https://blog.csdn.net/yangjiaer/article/details/131601302

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`timescale 1ns / 1ps
//
// Company:
// Engineer:
//
// Create Date: 20:20:58 04/21/2023
// Design Name:
// Module Name: CPU_design_experiments
// Project Name:
// Target Devices:
// Tool versions:
// Description:
//
// Dependencies:
//
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
//
//
module CPU_design_experiments(clk_M,SW,clk_im,rst_n,ZF,SF,CF,OF,seg,AN,Next_ST,w_data_s,MI,Inst_Code);//主模块
   input clk_im,rst_n,SW,clk_M;
   output ZF,SF,CF,OF,seg,AN,Next_ST,w_data_s,MI,Inst_Code;
   wire [7:0]PC_new,PC,PC0;
   wire [2:0]SW;
   wire [31:0]Inst_Code,R_Data_A,R_Data_B,F,imm32,M_R_Data,A,B,Data_B,Data_F,MDR,MI,IR,W_Data;
   wire [4:0]rs1,rs2,rd;
   wire [7:0]opcode,funct7;
   wire [2:0]funct3,bita;
   wire IS_R,IS_IMM,IS_LUI,PC_Write,IR_Write,Reg_Write,rs2_imm_s,ZF,SF,CF,OF,IS_LW,IS_SW,Mem_Write,clk_M,IS_BEQ,IS_JAL,IS_JALR;
   wire [1:0]w_data_s,PC_s;
   wire [3:0]ALU_OP,Next_ST;
   wire [7:0]seg;
   wire [3:0]AN;
   assign PC_new=PC+4;
   PC PC_n(rst_n,clk_im,PC_Write,PC_new,PC,imm32,F,PC0,PC_s);
   //c3 c3(PC_s,imm32,PC0,F,PC_new,PC);
   immPC0 immPC0(rst_n,clk_im,PC,PC0,PC0_Write);
   CPU_design_ROM ROM(clk_im,PC[7:2],Inst_Code);
   ID1 ID1(IR_Write,clk_im,Inst_Code,rs1,rs2,rd,opcode,funct3,funct7,IR);
   ID2 ID2(opcode,funct3,funct7,IS_R,IS_IMM,IS_LUI,ALU_OP,IS_LW,IS_SW,IS_BEQ,IS_JAL,IS_JALR);
   ImmU ImmU(clk_im,IR,imm32);
   CU CU(clk_im,rst_n,IS_R,IS_IMM,IS_LUI,PC_Write,IR_Write,Reg_Write,rs2_imm_s,w_data_s,IS_LW,IS_SW,Mem_Write,IS_BEQ,IS_JAL,IS_JALR,PC0_Write,PC_s,F,Next_ST);
   c4 c4(w_data_s,F,imm32,MDR,PC,W_Data);
   Register_heap heap(rst_n,Reg_Write,rs1,rs2,rd,W_Data,clk_im,R_Data_A,R_Data_B);
   immA immA(rst_n,clk_im,R_Data_A,A);
   immB immB(rst_n,clk_im,R_Data_B,B);
   ALU ALU(ALU_OP,A,Data_B,Data_F,ZF,SF,CF,OF);
   c2 c2(rs2_imm_s,Data_B,imm32,B);
   DM DM(Mem_Write,F,B,clk_im,M_R_Data);
   immF immF(rst_n,clk_im,Data_F,F);
   immMDR immMDR(rst_n,clk_im,M_R_Data,MDR);
   Delay_4ms Delay(clk_M,bita);
   c6 c6(SW,PC,IR,W_Data,A,B,F,MDR,MI,PC);
   Smg smg(MI,bita,seg,AN);
   //数码管显示还未设计
endmodule
module c3(PC_s,imm32,PC0,F,PC_new,PC);
   input PC_s,imm32,PC0,F,PC_new;
   output PC;
   wire [1:0]PC_s;
   wire [31:0]imm32,F,IM_Addr;
   wire [7:0]PC0;
   reg [31:0]PC;
   always@(*)
   case(PC_s)
   0:PC<=PC_new;
   1:PC<=imm32+PC0;
   2:PC<=F;
   endcase
endmodule
module c6(SW,PC,Inst_Code,W_Data,A,B,F,MDR,MI,Data_B);
   input SW,PC,Inst_Code,W_Data,A,B,F,MDR,Data_B;
   output MI;
   wire [2:0]SW;
   wire [31:0]PC,Inst_Code,W_Data,A,B,F,MDR,Data_B;
   reg [31:0]MI;
   always@(*)
   case(SW)
   0:MI<=PC;
   1:MI<=Inst_Code;
   2:MI<=W_Data;
   3:MI<=A;
   4:MI<=B;
   5:MI<=F;
   6:MI<=MDR;
   7:MI<=Data_B;
   endcase
endmodule
module c4(choose,A,B,C,D,M);
   input choose,A,B,C,D;
   output M;
   wire [1:0]choose;
   wire [31:0]A,B,C;
   wire [7:0]D;
   reg[31:0]M;
   always@(*)
   case(choose)
       0:M<=A;
       1:M<=B;
       2:M<=C;
       3:begin
       M[7:0]<=D;
       M[31:8]<=24'b0;
       end
   endcase
endmodule
module c2(rs2_imm_s,Data_B,imm32,B);
   input rs2_imm_s,imm32,B;
   output Data_B;
   reg [31:0]Data_B;
   wire [31:0]imm32,B;
   always@(*)
   case(rs2_imm_s)
   0:Data_B<=B;
   1:Data_B<=imm32;
   endcase
endmodule
module PC(rst_n,clk_im,PC_Write,IM_Addr,PC,imm32,F,PC0,PC_s);
   input rst_n,clk_im,PC_Write,IM_Addr,imm32,F,PC0,PC_s;
   output PC;
   wire [1:0]PC_s;
   wire [7:0]IM_Addr,PC0;
   wire [31:0]imm32,F;
   reg [7:0]PC;

   always@(posedge rst_n or negedge clk_im)
   begin
       if(rst_n)
       begin
           PC<=8'b00000000;
       end
       else
       begin
       if(PC_Write)
       case(PC_s)
           0:PC<=IM_Addr;
           1:PC<=(imm32<<2)+PC0;
           2:PC<=F;
       endcase
       end
   end
endmodule

module ID2(opcode,funct3,funct7,IS_R,IS_IMM,IS_LUI,ALU_OP,IS_LW,IS_SW,IS_BEQ,IS_JAL,IS_JALR);//指令二级译码1111111
   input[6:0]opcode;
   input[6:0]funct7;
   input[2:0]funct3;
   output IS_R,IS_IMM,IS_LUI,IS_LW,IS_SW,IS_BEQ,IS_JAL,IS_JALR;
   output [3:0]ALU_OP;
   reg IS_R,IS_IMM,IS_LUI,IS_LW,IS_SW,IS_BEQ,IS_JAL,IS_JALR;
   reg [3:0]ALU_OP;
   always@(*)
   begin
   case(opcode)
       7'b0110011://R型指令
           begin
               IS_R=1'b1;
               IS_IMM=1'b0;
               IS_LUI=1'b0;
               IS_LW=1'b0;
               IS_SW=1'b0;
               IS_BEQ=1'b0;
               IS_JAL=1'b0;
               IS_JALR=1'b0;
               ALU_OP={funct7[5],funct3};
           end
       7'b0010011://I型指令
           begin
               IS_R=1'b0;
               IS_IMM=1'b1;
               IS_LUI=1'b0;
               IS_LW=1'b0;
               IS_SW=1'b0;
               IS_BEQ=1'b0;
               IS_JAL=1'b0;
               IS_JALR=1'b0;
               ALU_OP=(funct3==3'b101)?{funct7[5],funct3}:{1'b0,funct3};
           end
       7'b0110111://U型指令
           begin
               IS_R=1'b0;
               IS_IMM=1'b0;
               IS_LUI=1'b1;
               IS_LW=1'b0;
               IS_SW=1'b0;
               IS_BEQ=1'b0;
               IS_JAL=1'b0;
               IS_JALR=1'b0;
           end
       7'b0000011://lw型指令
           begin
               IS_R=1'b0;
               IS_IMM=1'b0;
               IS_LUI=1'b0;
               IS_LW=1'b1;
               IS_SW=1'b0;
               IS_BEQ=1'b0;
               IS_JAL=1'b0;
               IS_JALR=1'b0;
               ALU_OP=4'b0000;
           end
       7'b0100011://sw型指令
           begin
               IS_R=1'b0;
               IS_IMM=1'b0;
               IS_LUI=1'b0;
               IS_LW=1'b0;
               IS_SW=1'b1;
               IS_BEQ=1'b0;
               IS_JAL=1'b0;
               IS_JALR=1'b0;
               ALU_OP=4'b0000;
           end
       7'b1100011://beq型指令
           begin
               IS_R=1'b0;
               IS_IMM=1'b0;
               IS_LUI=1'b0;
               IS_LW=1'b0;
               IS_SW=1'b0;
               IS_BEQ=1'b1;
               IS_JAL=1'b0;
               IS_JALR=1'b0;
               ALU_OP=4'b1000;
           end
       7'b1101111://jal型指令
           begin
               IS_R=1'b0;
               IS_IMM=1'b0;
               IS_LUI=1'b0;
               IS_LW=1'b0;
               IS_SW=1'b0;
               IS_BEQ=1'b0;
               IS_JAL=1'b1;
               IS_JALR=1'b0;
           end
       7'b1100111://jalr型指令
           begin
               IS_R=1'b0;
               IS_IMM=1'b0;
               IS_LUI=1'b0;
               IS_LW=1'b0;
               IS_SW=1'b0;
               IS_BEQ=1'b0;
               IS_JAL=1'b0;
               IS_JALR=1'b1;
               ALU_OP=4'b0000;
           end
   endcase
   end
endmodule
module CU(clk,rst_n,IS_R,IS_IMM,IS_LUI,PC_Write,IR_Write,Reg_Write,rs2_imm_s,w_data_s,IS_LW,IS_SW,Mem_Write,IS_BEQ,IS_JAL,IS_JALR,PC0_Write,PC_s,F,Next_ST);//CU控制单元模块
   input clk,rst_n,IS_R,IS_IMM,IS_LUI,IS_LW,IS_SW,IS_BEQ,IS_JAL,IS_JALR;
   input [31:0]F;
   //input [3:0]ALU_OP;
   output PC_Write,IR_Write,Reg_Write,rs2_imm_s,w_data_s,Mem_Write,PC0_Write,PC_s,Next_ST;
   //output [3:0]ALU_OP_o;
   reg [3:0]ST,Next_ST;
   reg PC_Write,IR_Write,Reg_Write,rs2_imm_s,PC0_Write;
   reg [1:0]w_data_s,PC_s;
   assign Mem_Write=(Next_ST==10);
   //reg [3:0]ALU_OP_o;
   always@(posedge rst_n or posedge clk)
       begin
           if(rst_n)ST<=0;
           else ST<=Next_ST;
       end
   always @(*)
       begin
           //assign Mem_Write=(Next_ST==10)
           Next_ST=0;
           case(ST)
               0:Next_ST=1;
               1:begin
                   if(IS_LUI)Next_ST=6;
                   else if(IS_JAL)Next_ST=11;
                   else Next_ST=2;
               end
               2:begin
                   if(IS_R)Next_ST=3;
                   else if(IS_IMM) Next_ST=5;
                   else if(IS_BEQ) Next_ST=13;
                   else Next_ST=7;
               end
               3:Next_ST=4;
               4:Next_ST=1;
               5:Next_ST=4;
               6:Next_ST=1;
               7:begin
                   if(IS_LW)Next_ST=8;
                   else if(IS_SW)Next_ST=10;
                   else Next_ST=12;
               end
               8:Next_ST=9;
               9:Next_ST=1;
               10:Next_ST=1;
               11:Next_ST=1;
               12:Next_ST=1;
               13:Next_ST=14;
               14:Next_ST=1;
           endcase
       end
   always@(posedge rst_n or posedge clk)
       begin
           if(rst_n)
               begin
               PC_Write<=0;
               IR_Write<=0;
               Reg_Write<=0;
               rs2_imm_s<=0;
               w_data_s<=0;
               end
           else
               begin
                   case(Next_ST)
                       1:
                           begin
                           PC_Write<=1;
                           PC0_Write<=1;
                           IR_Write<=1;
                           Reg_Write<=0;
                           PC_s<=0;
                           end
                       2:
                           begin
                           PC_Write<=0;
                           PC0_Write<=0;
                           IR_Write<=0;
                           Reg_Write<=0;
                           end
                       3:
                           begin
                           PC_Write<=0;
                           PC0_Write<=0;
                           IR_Write<=0;
                           Reg_Write<=0;
                           rs2_imm_s<=0;
                           end
                       4:
                           begin
                           PC_Write<=0;
                           PC0_Write<=0;
                           IR_Write<=0;
                           Reg_Write<=1;
                           w_data_s<=0;
                           end
                       5:
                           begin
                           PC_Write<=0;
                           PC0_Write<=0;
                           IR_Write<=0;
                           Reg_Write<=0;
                           rs2_imm_s<=1;
                           end
                       6:
                           begin
                           PC_Write<=0;
                           PC0_Write<=0;
                           IR_Write<=0;
                           Reg_Write<=1;
                           w_data_s<=1'b1;
                           end
                       7:
                           begin
                           PC_Write<=0;
                           PC0_Write<=0;
                           IR_Write<=0;
                           Reg_Write<=0;
                           rs2_imm_s<=1;
                           end
                       8:
                           begin
                           PC_Write<=0;
                           PC0_Write<=0;
                           IR_Write<=0;
                           Reg_Write<=0;
                           end
                       9:
                           begin
                           PC_Write<=0;
                           PC0_Write<=0;
                           IR_Write<=0;
                           Reg_Write<=1;
                           w_data_s<=2'b10;
                           end
                       10:
                           begin
                           PC_Write<=0;
                           PC0_Write<=0;
                           IR_Write<=0;
                           Reg_Write<=0;
                           end
                       11:
                           begin
                           PC_Write<=1;
                           PC0_Write<=0;
                           IR_Write<=0;
                           Reg_Write<=1;
                           w_data_s<=2'b11;
                           PC_s<=2'b01;
                           end
                       12:
                           begin
                           PC_Write<=1;
                           PC0_Write<=0;
                           IR_Write<=0;
                           Reg_Write<=1;
                           w_data_s<=2'b11;
                           PC_s<=2'b10;
                           end
                       13:
                           begin
                           PC_Write<=0;
                           PC0_Write<=0;
                           IR_Write<=0;
                           Reg_Write<=0;
                           rs2_imm_s<=0;
                           end
                       14:
                           begin
                           PC_Write<=(F==32'b0);//需改正
                           PC0_Write<=0;
                           IR_Write<=0;
                           Reg_Write<=0;
                           PC_s<=2'b01;
                           end
                   endcase
               end
           end
endmodule

module Register_heap(rst_n,Reg_Write,R_Addr_A,R_Addr_B,W_Addr,W_Data,clk_Regs,R_Data_A,R_Data_B);//寄存器堆设计
   input rst_n,Reg_Write,R_Addr_A,R_Addr_B,W_Addr,W_Data,clk_Regs;
   output R_Data_A,R_Data_B;
   wire [4:0] R_Addr_A,R_Addr_B,W_Addr;
   wire [31:0]W_Data;
   reg [31:0]R_Data_A,R_Data_B;
   reg [31:0]REG_Files[0:31];
   integer i;
   always @(posedge rst_n or negedge clk_Regs)
   begin
       if(rst_n)
           for(i=0;i<32;i=i+1)
               begin
                   REG_Files[i][31:0]<=0;
               end
       else
       begin
           if(!Reg_Write)
           begin
               R_Data_A<=REG_Files[R_Addr_A];
               R_Data_B<=REG_Files[R_Addr_B];
           end
           else
           begin
               REG_Files[W_Addr]<=W_Data;
           end
       end
   end
endmodule

module immA(rst_n,clk_im,R_Data_A,A);
   input rst_n,clk_im,R_Data_A;
   output A;
   wire [31:0]R_Data_A;
   reg [31:0]A;
   always @(posedge rst_n or negedge clk_im)
   begin
       if(rst_n)
           A<=32'b0;
       else
           A<=R_Data_A;
   end
endmodule

module immB(rst_n,clk_im,R_Data_B,B);
   input rst_n,clk_im,R_Data_B;
   output B;
   wire [31:0]R_Data_B;
   reg [31:0]B;
   always @(posedge rst_n or negedge clk_im)
   begin
       if(rst_n)
           B<=32'b0;
       else
           B<=R_Data_B;
   end
endmodule

module immPC0(rst_n,clk_im,PC,PC0,PC0_Write);
   input rst_n,clk_im,PC,PC0_Write;
   output PC0;
   wire [31:0]PC;
   reg [31:0]PC0;
   always @(posedge rst_n or negedge clk_im)
   begin
       if(rst_n)
           PC0<=32'b0;
       else
       if(PC0_Write)
           PC0<=PC;
   end
endmodule

module immF(rst_n,clk_im,R_Data_F,F);
   input rst_n,clk_im,R_Data_F;
   output F;
   wire [31:0]R_Data_F;
   reg [31:0]F;
   always @(posedge rst_n or negedge clk_im)
   begin
       if(rst_n)
           F<=32'b0;
       else
           F<=R_Data_F;
   end
endmodule

module ID1(IR_Write,clk_im,inst,rs1,rs2,rd,opcode,funct3,funct7,IR);//译码
   input IR_Write,inst,clk_im;
   output opcode,funct3,funct7,IR;
   wire [31:0]inst;
   output reg[4:0]rs1,rs2,rd;
   reg[6:0]opcode,funct7;
   reg[2:0]funct3;
   reg [31:0]IR;
   always@(negedge clk_im)
   if(IR_Write)
       begin
           IR<=inst;
           funct7<=inst[31:25];
           rs2<=inst[24:20];
           rs1<=inst[19:15];
           funct3<=inst[14:12];
           rd<=inst[11:7];
           opcode<=inst[6:0];
       end
endmodule

module ImmU(clk_im,inst,imm32);//生成立即数
   input clk_im,inst;
   output imm32;
   wire [31:0]inst;
   reg [31:0]imm32;
   always@(*)
   begin
       case(inst[6:0])
           7'b0010011:begin
           if(inst[31:25]==7'b0000000)imm32<={{27{0}},inst[24:20]};
           else imm32<={{20{inst[31]}},inst[31:20]};//I型指令
           end
           7'b0110111:begin
           imm32<={{1{inst[31]}},inst[30:12],12'b0};
           end//U型指令
           7'b0000011:imm32<={{27{0}},inst[24:20]};
           7'b0100011:imm32<={{20{inst[31]}},inst[31:25],inst[11:7]};//S型指令
           7'b1100011:imm32<={{20{inst[31]}},inst[7],inst[30:25],inst[11:8],1'b0};//B型指令
           7'b1101111:imm32<={{14{inst[31]}},inst[19:12],inst[20],inst[30:22]};//J型指令
       endcase
   end
endmodule

module ALU(input [3:0]ALU_OP,input [31:0]A,input [31:0]B,output reg[31:0]F,output reg ZF,output reg SF,output reg CF,output reg OF);//实现ALU 10种功能
   reg signed [31:0]a,b;//定义有符号数据
   initial
   begin
   a=$signed(A);
   b=$signed(B);
   end
   reg c32;
   always@(*)
       begin
           case(ALU_OP)
               4'b0000:{c32,F}<=A+B;
               4'b0001:F<=A<<B;
               4'b0010:F <= (a<b) ? 1 : 0 ;//有符号
               4'b0011:F <= (A<B) ? 1 : 0 ;
               4'b0100:F<=A^B;
               4'b0101:F<=A>>B;
               4'b0110:F<=A|B;
               4'b0111:F<=A&B;
               4'b1000:{c32,F}<=A-B;
               4'b1101:F<=a>>>b;//有符号
           endcase
           if(F==32'h00000000)ZF<=0;
           else ZF<=1;
           SF<=F[31];
           if(ALU_OP==4'b0000)CF<=c32;
           else if(ALU_OP==4'b1000)CF<=~c32;
           else ;
           OF<=c32^F[31]^A[31]^B[31];
       end
endmodule

module DM(Mem_Write,DM_Addr,M_W_Data,clk_dm,M_R_Data);//数据存储模块
   input Mem_Write,DM_Addr,M_W_Data,clk_dm;
   output M_R_Data;
   wire [31:0]DM_Addr,M_W_Data;
   wire [31:0]M_R_Data;
   Data_memory D(clk_dm,Mem_Write,DM_Addr[5 : 0],M_W_Data,M_R_Data);
endmodule
module immMDR(rst_n,clk_im,M_R_Data,MDR);
   input rst_n,clk_im,M_R_Data;
   output MDR;
   wire [31:0]M_R_Data;
   reg [31:0]MDR;
   always @(posedge rst_n or negedge clk_im)
   begin
       if(rst_n)
           MDR<=32'b0;
       else
           MDR<=M_R_Data;
   end
endmodule
module Delay_4ms(
   input wire clk_M,
   output reg [2:0]bita
   );
   reg [15:0]counter;
   initial
   begin
   bita = 3'd0;
   counter=16'd0;
   end
   always@(posedge clk_M)
       begin
           counter<=counter+1'b1;
           if(counter==16'd50000)
               begin
                   bita<=bita+1'b1;
                   counter<=16'd0;
               end
           end
endmodule

//数码管显示
module Smg(
   input wire [31:0]F,
   input wire [2:0]bita,
   output reg [7:0]seg,
   output reg [3:0]AN
);
   reg [3:0] data_now;
   reg [7:0] duan;
   initial
       begin
           data_now=4'b0;
           duan=8'b0;
       end

   always@(*)
       begin
           case(bita)
               0:AN<=4'b1111;
               1:AN<=4'b1110;
               2:AN<=4'b1101;
               3:AN<=4'b1100;
               4:AN<=4'b1011;
               5:AN<=4'b1010;
               6:AN<=4'b1001;
               7:AN<=4'b1000;
           endcase
       end
   always@(*)
       begin
               case(bita)
                       0:data_now[3:0]<=F[3:0];
                       1:data_now[3:0]<=F[7:4];
                       2:data_now[3:0]<=F[11:8];
                       3:data_now[3:0]<=F[15:12];
                       4:data_now[3:0]<=F[19:16];
                       5:data_now[3:0]<=F[23:20];
                       6:data_now[3:0]<=F[27:24];
                       7:data_now[3:0]<=F[31:28];
               endcase
       end
   always@(*)
       begin
               case(data_now[3:0])
                       0:seg[7:0]<=8'b00000011;
                       1:seg[7:0]<=8'b10011111;
                       2:seg[7:0]<=8'b00100101;
                       3:seg[7:0]<=8'b00001101;
                       4:seg[7:0]<=8'b10011001;
                       5:seg[7:0]<=8'b01001001;
                       6:seg[7:0]<=8'b01000001;
                       7:seg[7:0]<=8'b00011111;
                       8:seg[7:0]<=8'b00000001;
                       9:seg[7:0]<=8'b00001001;
                       4'b1010:seg[7:0]<=8'b00010001;
                       4'b1011:seg[7:0]<=8'b11000001;
                       4'b1100:seg[7:0]<=8'b01100011;
                       4'b1101:seg[7:0]<=8'b10000101;
                       4'b1110:seg[7:0]<=8'b01100001;
                       4'b1111:seg[7:0]<=8'b01110001;
               endcase
       end
endmodule

管脚代码：

NET "AN[3]" IOSTANDARD = LVCMOS18;
NET "AN[2]" IOSTANDARD = LVCMOS18;
NET "AN[1]" IOSTANDARD = LVCMOS18;
NET "AN[0]" IOSTANDARD = LVCMOS18;
NET "seg[7]" IOSTANDARD = LVCMOS18;
NET "seg[6]" IOSTANDARD = LVCMOS18;
NET "seg[5]" IOSTANDARD = LVCMOS18;
NET "seg[4]" IOSTANDARD = LVCMOS18;
NET "seg[3]" IOSTANDARD = LVCMOS18;
NET "seg[2]" IOSTANDARD = LVCMOS18;
NET "seg[1]" IOSTANDARD = LVCMOS18;
NET "seg[0]" IOSTANDARD = LVCMOS18;
NET "SW[2]" IOSTANDARD = LVCMOS18;
NET "SW[1]" IOSTANDARD = LVCMOS18;
NET "SW[0]" IOSTANDARD = LVCMOS18;
NET "CF" IOSTANDARD = LVCMOS18;
NET "clk_im" IOSTANDARD = LVCMOS18;
NET "clk_M" IOSTANDARD = LVCMOS18;
NET "OF" IOSTANDARD = LVCMOS18;
NET "rst_n" IOSTANDARD = LVCMOS18;
NET "SF" IOSTANDARD = LVCMOS18;
NET "ZF" IOSTANDARD = LVCMOS18;
NET "SW[2]" PULLDOWN;
NET "SW[1]" PULLDOWN;
NET "SW[0]" PULLDOWN;
NET "clk_im" PULLDOWN;
NET "clk_M" PULLDOWN;
NET "rst_n" PULLDOWN;

NET "clk_M" LOC = H4;
NET "rst_n" LOC = R4;
NET "clk_im" LOC = AA4;
NET "AN[3]" LOC = L21;
NET "AN[2]" LOC = M22;
NET "AN[1]" LOC = M21;
NET "AN[0]" LOC = N22;
NET "seg[7]" LOC = H19;
NET "seg[6]" LOC = G20;
NET "seg[5]" LOC = J22;
NET "seg[4]" LOC = K22;
NET "seg[3]" LOC = K21;
NET "seg[2]" LOC = H20;
NET "seg[1]" LOC = H22;
NET "seg[0]" LOC = J21;
NET "SW[2]" LOC = U7;
NET "SW[1]" LOC = AB7;
NET "SW[0]" LOC = AB8;
NET "CF" LOC = R1;
NET "OF" LOC = P2;
NET "SF" LOC = P1;
NET "ZF" LOC = N2;
NET "clk_im" CLOCK_DEDICATED_ROUTE = FALSE;

NET "Next_ST[3]" LOC = H3;
NET "Next_ST[2]" LOC = N4;
NET "Next_ST[1]" LOC = L4;
NET "Next_ST[0]" LOC = J4;

NET "Next_ST[3]" IOSTANDARD = LVCMOS18;
NET "Next_ST[2]" IOSTANDARD = LVCMOS18;
NET "Next_ST[1]" IOSTANDARD = LVCMOS18;
NET "Next_ST[0]" IOSTANDARD = LVCMOS18;

NET "w_data_s[1]" LOC = K4;
NET "w_data_s[0]" LOC = G4;

# PlanAhead Generated IO constraints

NET "w_data_s[1]" IOSTANDARD = LVCMOS18;
NET "w_data_s[0]" IOSTANDARD = LVCMOS18;