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MPC866 Applications Development System (ADS)
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MPC866ADS New Mode (EDO DRAM is not used)
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writereg IMMR 0xFF000000
writemmr SYPCR 0xFFFFFF88
writemmr SIUMCR 0x01012440
writereg MSR 0x00001002
writereg SRR1 0x00001002
writereg ICTRL 0x00000007
writemmr PLPRCRK 0x55CCAA33 # Unlock PLPRCR Register
writemmr PLPRCR 0x006a0000 # PLPRCR 25MHz
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UPMB Initialization for SDRAM
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Single Read
writeupmb 0x00 0x0126cc04
writeupmb 0x01 0x0fb98c00
writeupmb 0x02 0x1ff74c45
writeupmb 0x03 0xffffffff
writeupmb 0x04 0xffffffff
writeupmb 0x05 0x1fe77c34
writeupmb 0x06 0xefaabc34
writeupmb 0x07 0x1fa57c35
Burst Read
writeupmb 0x08 0x0026fc04
writeupmb 0x09 0x10adfc00
writeupmb 0x0A 0xf0affc00
writeupmb 0x0B 0xf1affc00
writeupmb 0x0C 0xefbbbc00
writeupmb 0x0D 0x1ff77c45
writeupmb 0x0E 0xffffffff
writeupmb 0x0F 0xffffffff
writeupmb 0x10 0xffffffff
writeupmb 0x11 0xffffffff
writeupmb 0x12 0xffffffff
writeupmb 0x13 0xffffffff
writeupmb 0x14 0xffffffff
writeupmb 0x15 0xffffffff
writeupmb 0x16 0xffffffff
writeupmb 0x17 0xffffffff
Single Write
writeupmb 0x18 0x0e26bc04
writeupmb 0x19 0x01b93c00
writeupmb 0x1A 0x1ff77c45
writeupmb 0x1B 0xffffffff
writeupmb 0x1C 0xffffffff
writeupmb 0x1D 0xffffffff
writeupmb 0x1E 0xffffffff
writeupmb 0x1F 0xffffffff
Burst Write
writeupmb 0x20 0x0e26bc00
writeupmb 0x21 0x10ad7c00
writeupmb 0x22 0xf0affc00
writeupmb 0x23 0xf0affc00
writeupmb 0x24 0xe1bbbc04
writeupmb 0x25 0x1ff77c45
writeupmb 0x26 0xffffffff
writeupmb 0x27 0xffffffff
writeupmb 0x28 0xffffffff
writeupmb 0x29 0xffffffff
writeupmb 0x2A 0xffffffff
writeupmb 0x2B 0xffffffff
writeupmb 0x2C 0xffffffff
writeupmb 0x2D 0xffffffff
writeupmb 0x2E 0xffffffff
writeupmb 0x2F 0xffffffff
Refresh
writeupmb 0x30 0x1ff5fc84
writeupmb 0x31 0xfffffc04
writeupmb 0x32 0xfffffc84
writeupmb 0x33 0xfffffc05
writeupmb 0x34 0xffffffff
writeupmb 0x35 0xffffffff
writeupmb 0x36 0xffffffff
writeupmb 0x37 0xffffffff
writeupmb 0x38 0xffffffff
writeupmb 0x39 0xffffffff
writeupmb 0x3A 0xffffffff
writeupmb 0x3B 0xffffffff
Exception
writeupmb 0x3C 0x7ffffc07
writeupmb 0x3D 0xffffffff
writeupmb 0x3E 0xffffffff
writeupmb 0x3F 0xffffffff
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Set up the chip selects for flash, RAM, and board control regs
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writemmr MBMR 0x60802114 # MBMR - 25MHz
writemmr MPTPR 0x0400
CS0 - FLASH - base 0xFFE00000, 32 bit port size, GPCM
CS0 - FLASH - base 0x02800000, 32 bit port size, GPCM
writemmr BR0 0xFFe00001
writemmr BR0 0x02800001
writemmr OR0 0xFFE00D34 # 2MB block size, 2ws (MCM29F040-90)
writemmr OR0 0xFFE00D34 # 2MB block size, 2ws (MCM29F040-90)
CS1 - BCSR - base 0xf0000000, 32 bit port size, GPCM
writemmr BR1 0xf0000001 # BR1
writemmr OR1 0xffff8110 # OR1
CS2 - invalidate the DRAM SIMM bank
writemmr BR2 0x00000088 # Machine select for DRAM-EDO is reserved and the bank is invalid
writemmr OR2 0xFFC00800 # MCM36100/200-60/70
CS3 - DRAM SIMM
writemmr BR3 0x00400088 # BR3 - Machine select for DRAM-EDO is reserved and the bank is invalid
writemmr OR3 0xFFC00800 # OR3 - 4MB
writemmr BR3 0x01000088 # BR3 - Machine select for DRAM-EDO is reserved and the bank is invalid
writemmr OR3 0xFF000800 # OR3 - 16MB
CS4 - SDRAM - base 0x03000000, UPMB
writemmr BR4 0x000000C1
writemmr OR4 0xFF800A00 # 8MB SDRAM
CS5 - comm peripheral
writemmr BR5 0x02000401
writemmr OR5 0xFFF009A6
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SDRAM initialization
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writemmr MAR 0x00000048 # MAR = 0x48
writemmr MCR 0x80808105 # MCR = 0x80808105
writemmr MBMR 0x60802118 # Set TFLB field of MBMR to 8
writemmr MCR 0x80808130 # MCR = 0x80808130
writemmr MBMR 0x60802114 # Restore original MBMR
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The debugger sets the DER register based on the EPPC Exceptions
preference panel after running this initialization file, this
this value will be overwritten. We only put it in here because
the flash programmer uses this file also.
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writereg DER 0x73e67c0f