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verilog
云朵甜不甜
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卡诺图化简
自用记录,更多详情请见https://blog.csdn.net/hahasusu/article/details/88244155画出逻辑函数的卡诺图化简圈越大越好,越少越好,圈内元素2n个Eg.左错,右对原创 2021-03-23 09:48:58 · 636 阅读 · 0 评论 -
HDLBits:Edgedetect
EdgedetectFor each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.Here are some examples.原创 2021-03-24 11:14:01 · 2360 阅读 · 0 评论 -
补码相加及判断溢出
方法一:若符号位发生进位则Cs=1,否则为0若最高数值为发生进位则Cp=1,否则为0方法二:符号位0(正数),符号位1(负数)a[7] && b[7] && ~s[7]:正数相加产生一个负数,判断溢出。~a[7] && ~b[7] && s[7]:负数相减(补码相加)产生正数,判断溢出。module top_module ( input [7:0] a, input [7:0] b, output [原创 2021-03-22 11:53:44 · 3471 阅读 · 0 评论