HDLBits：Edgedetect

最新推荐文章于 2024-08-13 09:33:01 发布

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最新推荐文章于 2024-08-13 09:33:01 发布

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Edgedetect
For each bit in an 8-bit vector, detect when the input signal changes from 0 in one clock cycle to 1 the next (similar to positive edge detection). The output bit should be set the cycle after a 0 to 1 transition occurs.
Here are some examples. For clarity, in[1] and pedge[1] are shown separately.
在这里插入图片描述
检测输入信号从0跳变到1的位置

module top_module (
    input clk,
    input [7:0] in,
    output [7:0] pedge
);
    reg [7:0] in_state;
    always@(posedge clk)
        begin
            in_state<=in;
            pedge<=in&~in_state;
        end
endmodule