本文主要介绍基于vivado平台,搭建出一位全加器和四位全加器的代码,及其例化方式,以及激励文件调用。
一位全加器的代码编写如下:
module fulladd(sum,c_out,a,b,c_in);
output sum, c_out;
input a,b,c_in;
wire s1,c1,c2;
xor (s1,a,b);
and (c1,a,b);
xor (sum,s1,c_in);
and (c2,s1,c_in);
xor(c_out,c2,c1);
endmodule
四位全加器代码如下:
module fulladd4(sum,c_out,a,b,c_in);
output [3:0] sum;
output c_out;
input [3:0] a,b;
input c_in;
wire c1,c2,c3;
fulladd fa0(sum[0],c1,a[0],b[0],c_in);
fulladd fa1(sum[1],c2,a[1],b[1],c1);
fulladd fa2(sum[2],c3,a[2],b[2],c2);
fulladd fa3(sum[3],c_out,a[3],b[3],c3);
endmodule
激励函数代码的编写:
module stimulus;
reg [3:0] A,B;
reg C_IN;
wire [3:0] SUM;
wire C_OUT;
//调用一位全加器模块
fulladd4 FA1_4(SUM,C_OUT,A,B,C_IN);
//设计信号值的监视
initial begin
$monitor($time,"A= %b, B= %b, C_IN = %b, --- C_OUT= %b,SUM= %b",A,B,C_IN,C_OUT,SUM);
end
initial begin
A = 4'd0; B= 4'd0; C_IN=1'd0;
#5 A = 4'd2; B= 4'd1;
#5 A = 4'd5; B= 4'd3;
#5 A = 4'd6; B= 4'd1;
#5 A = 4'd1; B= 4'd2;
#5 A = 4'd3; B= 4'd2;
3
end
endmodule
仿真结果
![](https://img-blog.csdnimg.cn/img_convert/cbc541fdc9e7af5badfe65e5995ea4bd.png)
仿真结果
# run 1000ns
0A= 0000, B= 0000, C_IN = 0, --- C_OUT= 0,SUM= 0000
5A= 0010, B= 0001, C_IN = 0, --- C_OUT= 0,SUM= 0011
10A= 0101, B= 0011, C_IN = 0, --- C_OUT= 0,SUM= 1000
15A= 0110, B= 0001, C_IN = 0, --- C_OUT= 0,SUM= 0111
20A= 0001, B= 0010, C_IN = 0, --- C_OUT= 0,SUM= 0011
25A= 0011, B= 0010, C_IN = 0, --- C_OUT= 0,SUM= 0101