TI C66x DSP 系统events及其应用 - 4.3（Exception handle）

下面介绍下在CPU内部怎么处理exception。根据下图EFR寄存器记录了（首先要使能exception，否侧EFR不能记录，见英文描述）CPU检测到的exception类型，当检测到NMI，NXF位会被置位，当检测到excepton（event4~127 trigger），EXF位会被置位等。在用户模式下，EFR寄存器不可访问，在spervisor模式下，可以通过MVC EFR访问。

EXCEP is the maskable external exception input to the CPU. It is enabled by the XEN bit in TSR. For this exception to be recognized, the XEN bit must be set to 1, the GEE bit must be set to 1, and the NMIE bit must be set to 1.When EXCEP is recognized as pending, the external exception flag (EXF) bit in EFR is set. The EXF bit remains set until manually cleared in the exception service routine.

当硬件检测到EFR寄存器被置位，如EXF位会被置为1，经过几个cycle后（硬件延迟）硬件通知CPU，CPU就会执行与EXCEP绑定的vector（包含跳转指令），进而跳转到excepton handler函数执行。如下面的callStack中，exception发生后，进入vector1，然后执行ExceptionHandlerEsr函数处理exception。                       

TI DSP C66x DSP exception callStack:
1082a760:_ZN13PuschReceiver25CPuschChannelRawEstimator11EstimateSnrEPPjP18SPuschUeReceiveReqPPfS6_S6_S6_h  (offset = 000000a0)
1083ed74:_ZN13PuschReceiver28CPuschReceiverEstAlgoCtrller14RefSymEstimateEhthh  (offset = 000006d4)
10800020:_vector1                                    (offset = 00000000)
8202ee60:platform_ErrorDriver_code                   (offset = 00000000)
8202cba0:ExceptionHandlerEsr                         (offset = 00000000)
82033ef0:ExceptionHandlerEnableSingleEventException  (offset = 00000190)

EFR寄存器: