Pandoras Box

#define ACCESS_ONCE(x) (*(volatile typeof(x) *)&(x))//volatile确保不被编译器优化省略，且每次必须直接从内存读值#define DEFINE_PER_THREAD(type, name) \        struct { \                __typeof__(type) v \

超线程是利用

The store buffer is associated with the processors instruction execution units. Itallows writes to system memory and/or the internal caches to be saved and in somecases combined to optimize the pr

Instruction Reordering有两种，包括Compiler Reordering和Memory Reordering。  Intel官方列出的有关Memory Reordering的情况总共有8种：  Neither Loads Nor Stores Are Reordered with Like Operations  Stores Are Not Reor

Many modern microprocessors implement store buffer forwarding which is a mechanism that improves microprocessor performance by completing a younger dependent load operation by using data from an old

Reprint:http://www.ibm.com/developerworks/systems/articles/powerpc.htmlThe barrier created by the sync instruction is more comprehensive in that it orders all storage accesses regardless of class.

Reprint：http://www.surf.org.uk/articles/CISC_vs._RISC.htmlRISC architectures lend themselves more towards pipelining than CISC architectures for many reasons. As RISC architectures have a smalle

Reprint：http://preshing.com/20111124/always-use-a-lightweight-mutexIn multithreaded programming, we often speak of locks (also known as mutexes). But a lock is only a concept. To actually use 

关于 Acqurie Semantics 和 Release Semantics 的解释，感觉MSDN上的解释最容易理解：（http://msdn.microsoft.com/en-us/library/ff540496.aspx）An operation has acquire semantics if other processors will always see its e

Reprint:http://www.tomshardware.com/forum/342869-28-difference-processor-coreThe terms 'Processor', 'Core', and 'CPU' are all poorly defined and have undergone many changes in meaning over the y

Reprint：http://preshing.com/20121019/this-is-why-they-call-it-a-weakly-ordered-cpuOn this blog, I’ve been rambling on about lock-free programming subjects such as acquire and release semanti

ARM is a RISC (Reduced Instruction Set Computing) architecture while x86 being a CISC (Complex Instruction Set Computing) one.ARM is a RISC (Reduced Instruction Set Computing) archit

转自unbutun的博客：http://blog.csdn.net/unbutun/article/details/6123472gcc内嵌汇编简介在内嵌汇编中，可以将C语言表达式指定为汇编指令的操作数，而且不用去管如何将C语言表达式的值读入哪个寄存器，以及如何将计算结果写回C 变量，你只要告诉程序中C语言表达式与汇编指令操作数之间的对应关系即可， GCC会自动插入代码完成必要的操

Reprint：http://strupat.ca/2010/10/cross-platform-function-to-get-the-line-size-of-your-cache/  注意获得的cache line大小单位为字节。#ifndef GET_CACHE_LINE_SIZE_H_INCLUDED#define GET_CACHE_LINE_SIZE_H_INC

有的时候，使用多线程的速度