Port declarations
may be written differently when using Verilog 2001 compared to Verilog 95
Verilog 95
module top (...q);
:
output q;
reg q;
Verilog 2001
module top (...q);
:
output reg q;
or
module top (... output reg q);
Always Statements may be written differently when using Verilog 2001 compared to Verilog 95Verilog 95
always @(a or b or c)
begin
:
Verilog 2001
always @(a, b, c)
begin
:
or
always @*
begin
:
or
always @(*)
begin
: