kinetis之 KV46F150M 的ADC模块使用小结
kinetis系列 ADC 操作大多相同, 不如 MK60 MK10 以及 KV31 等 ,但KV46 的ADC外设的寄存器组织却完全不同于其他 :
- 相关代码如下
初始化代码 :
/***********************************************************************************************
** Function name: adcInit
** Descriptions: Initialization of the PDB and A/D converter for current and voltage sensing
** input parameters: 根据需要自行查阅芯片手册,修改配置相关寄存器.
** output parameters:
** Returned value:
**
** Created by: liGuangdao
** Created Date: 2016/7/13 星期三
**——————————————————————————————————–
** Modified by:
** Modified date:
***********************************************************************************************/
void adcInit(void)
{
/* ### ADC init code */
// enable clock for ADC module
SIM_SCGC5 |= SIM_SCGC5_ADC_MASK;
/* SMODE - triggered parallel, SYNC0 - enabled, interrupt 25MHz */
ADC_CTRL1 = ADC_CTRL1_STOP0_MASK | ADC_CTRL1_SMODE(4)|ADC_CTRL1_EOSIE0_MASK|ADC_CTRL1_SYNC0_MASK;
ADC_CTRL2 = ADC_CTRL2_STOP1_MASK | ADC_CTRL2_DIV0(0x05)|ADC_CTRL2_EOSIE1_MASK; /* ; */
/*
ADC_CTRL2_SIMULT_MASK
*/
/*
* ADC_CLIST1 = 0x3210;
* ADC_CLIST2 = 0x7654;
* ADC_CLIST3 = 0xBA88;
* ADC_CLIST4 = 0xFEDC;
* 采集通道 ADCA_CH0 ADCA_CH1 ADCB_CH0 ADCB_CH1;
*/
ADC_CLIST1 = ADC_CLIST1_SAMPLE0(0) | ADC_CLIST1_SAMPLE1(1) |
ADC_CLIST1_SAMPLE2(8) | ADC_CLIST1_SAMPLE3(9);
ADC_CLIST3 = ADC_CLIST3_SAMPLE8(9);
/*
*采样序列中,仅仅打开 0 1 2 8 位置
*/
ADC_SDIS = 0xfff8; /* 1111_1111_1111_0000 */
ADC_ZXSTAT = ADC_ZXSTAT_ZCS(0xFFFF); /* Clear zero crossing status flags */
ADC_LOLIMSTAT = ADC_LOLIMSTAT_LLS(0xFFFF); /* Clear low limit status */
ADC_HILIMSTAT = ADC_HILIMSTAT_HLS(0xFFFF); /* Clear high limit status */
ADC_STAT = ADC_STAT_EOSI1_MASK | ADC_STAT_EOSI0_MASK; /* Clear EOSI and EOSI1 flags */
/*
* Interrupt don’t occcur when in converting sample(not complete )
* The relevent bits to select the samples that will generate a scan interupt
* I don’t know why the will a default isr vector3 entance when config the reigster = 0 yizhi
*/
//ADC_SCHLTEN = 0;
ADC_SCTRL = 0; /* No stop waite for Sync slot */
/* power-up delay set to 26 clocks */
ADC_PWR = 0x01A0U;
/* ADCA Speed <=25MHz; ADCB Speed<=25MHz; DIV1 = 6, 25 MHz */
ADC_PWR2 = ADC_PWR2_SPEEDA(3) | ADC_PWR2_SPEEDB(3) | ADC_PWR2_DIV1(5);
SIM_SCGC5 |= SIM_SCGC5_XBARA_MASK; /* Enable clock for XBARA module */
/*
* FTM0 INIT to ADC0
* XBARA_IN17 (FTM0_INIT) —> XBARA_OUT12(ADCA_TRIG) reference the user manual P.485
*/
XBARA_SEL6 = XBARA_SEL6_SEL12(17);
while(ADC_PWR & (ADC_PWR_PSTS0_MASK|ADC_PWR_PSTS1_MASK)){}; /* wait for ADC to power up */
ADC_CTRL1 &= ~ADC_CTRL1_STOP0_MASK;
ADC_CTRL2 &= ~ADC_CTRL2_STOP1_MASK;
PORTE_PCR16 = PORT_PCR_MUX(0); /* ADCA_CH0 */
PORTE_PCR17 = PORT_PCR_MUX(0); /* ADCA_CH1 */
PORTE_PCR18 = PORT_PCR_MUX(0); /* ADCB_CH0 */
PORTE_PCR19 = PORT_PCR_MUX(0); /* ADCB_CH1 */
//ISR_ENABLE_VECT(55);
}
使用上述代码进行初始化KV46的ADC 模块
1, 打开ADC模块的时钟,
2, 配置 ADC_CTRL1 ADC_CTRL2 ,设置 ADC转换的模式,MODE,时钟等
3, CLIST1 CLIST2 确定要转换的slots 设置 掩码寄存器.
4,其他设置详见代码
/*********************************************************************************************************
** Function name: kv4xAdcRsltGet
** Descriptions: none
** input parameters: 若使用该函数读取单个通道的AD值,最好采用parallel模式,这样ADCA和ADCB是分开的。
** output parameters: 注意在这种paralle模式下 ADC_CLIST1 ADC_CLIST2(ADCA)、ADC_CLIST3 ADC_CLIST4(ADCB)
** Returned value: 并不是随便设置的,ADC_CLIST1 ADC_CLIST2只能设置(ch0-CH7) ADC_CLIST3 ADC_CLIST4只能
** 设置(ch8-ch15).
** Created by: liGuangdao
** Created Date: 2016/7/13 星期三
**--------------------------------------------------------------------------------------------------------
** Modified by:
** Modified date:
*********************************************************************************************************/
uint16_t kv4xAdcRsltGet(ADCX_e adc,uint8_t slo)
{
if(adc == ADCA)
ADC_CTRL1 |= ADC_CTRL1_START0_MASK;/* software start the sample */
else
ADC_CTRL2 |= ADC_CTRL2_START1_MASK;
while((ADC_RDY & (1<<slo))==0); /* waite the slot is completed */
return ((ADC_RSLT_REG(ADC_BASE_PTR,slo) & ADC_RSLT_RSLT_MASK) >> ADC_RSLT_RSLT_SHIFT);
}
1, sequencial 和parallel 模式, 在 sequencial 模式下 ,两个ADC模块 公用一套设置, 就是 CTRL1, 此时设置CTRl2 不起作用
2, 其中在 parallel模式下可以带卡 simultaneous,实现两个通道同时转换
3,在paralle模式下 ADC_CLIST1 ADC_CLIST2(ADCA)、ADC_CLIST3 ADC_CLIST4(ADCB) 并不是随便设置的,ADC_CLIST1 ADC_CLIST2只能设置(ch0-CH7) ADC_CLIST3 ADC_CLIST4只能 设置(ch8-ch15). 而在sequencial模式下没有这个要求
3, 当MODE 我 1 或者 2 时 若使能触发(同步 sync),则只会触发一次,