Division (除法器)

最新推荐文章于 2024-03-25 14:08:19 发布

SEU-RC

最新推荐文章于 2024-03-25 14:08:19 发布

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分类专栏： Verilog HDL Examples 文章标签： reference integer output module div

本文链接：https://blog.csdn.net/chevroletss/article/details/6308399

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这个Verilog代码实现了一个无符号整数除法器，通过减法和左移来完成除法操作。当除数为0时，会设置错误标志；当除法完成后，准备好标志被置位。代码包括状态机逻辑，用于处理除法过程，并提供了测试激励进行仿真验证。

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Reference：

“Digital design and principles and practices”, John F. Wakerly

“Advanced Digital Design with Verilog HDL”, Michael D.Ciletti

`timescale 1ns / 1ps // // Company: SEU.IC // Engineer: Ray // Description: // 1, this verilog code is designed for unsigned integer division; // 2, subtract_and_shift --> division; // 3, word1_in/word2_in = quotient + remainder; // 4, word1_in is the dividend and word2_in is the divisor; // 5, if word2_in == 'd0, then set the error_out; // 6, ready_out is utilized to indicate the completion of division // 7, the width of word2_in is not larger than the width of word1_in; // 8, the subtraction is realized by 2s complement addition // module division_4( quotient_out, remainder_out, ready_out, error_out, word1_in, word2_in, start_in, clock, reset); p