module arm_iic_reg_top( inout f_iic_sda, input f_iic_scl, //iic�ӿڴ�����Ϣ input sys_clk, input [7:0] data_in0, //��ַ0����λ���������͵����� �������� input [7:0] data_in1, //ͬ�� onebit_to_dac1����ѡ�� input [7:0] data_in2, // eightbit_to_dac1����ѡ�� input [7:0] data_in3, // dac_out1����ѡ�� input [7:0] data_in4, input [7:0] data_in5, input [7:0] data_in6, input [7:0] data_in7, input [7:0] data_in8, input [7:0] data_in9, output [7:0] data_out0, //��λ����������ַ0���͵����� output [7:0] data_out1, output [7:0] data_out2, output [7:0] data_out3, output [7:0] data_out4, output [7:0] data_out5, output [7:0] data_out6, output [7:0] data_out7, output [7:0] data_out8, output [7:0] data_out9 ); arm_iic_reg arm_iic_reg_inst0 ( .f_iic_sda (f_iic_sda), .f_iic_scl (f_iic_scl), .sys_rst (1'b1), .sys_clk (sys_clk), .data_in0 (0), .data_in1 (0), .data_in2 (0), .data_in3 (1), .data_in4 (data_in4), .data_in5 (data_in5), .data_in6 (data_in6), .data_in7 (data_in7), .data_in8 (data_in8), .data_in9 (data_in9), .data_reg0 (data_out0), .data_reg1 (data_out1), .data_reg2 (data_out2), .data_reg3 (data_out3), .data_reg4 (data_out4), .data_reg5 (data_out5), .data_reg6 (data_out6), .data_reg7 (data_out7), .data_reg8 (data_out8), .data_reg9 (data_out9) ); endmodule
最新发布