LCD和平台的RGB时序要匹配才可点亮LCD,其实为了兼容不同的lcd,一般平台这边的lcdc时序不做改动,而去修改LCD侧的设置(可以修改初始化寄存器列表)来适应平台的lcdc.但是如果LCD不能修改,就只能修改平台这边的了。本文以RGB中的VSYNC HSYNC DEN这三个信号极性为例,介绍如何设置平台侧lcdcontroller的timing,以下是从高通文档中摘出来的内容。
HARDWARE
(以下内容来自80-VM155-25MSM7X27A-MSM7X25A CHIPSET TRAINING_ BASEBAND TOPICS.pdf)
LCD Controller Tuning
The behavior of the RGB interface mustbe tuned to match the characteristics of the panel
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Parameters such as resolution,refresh rate, horizontal and vertical blanking and color depth, mustall be identified, determined, and properly set in the relevantLCDC registers of the
MSM7x27A/MSM7x25A IC.
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List of tunable paramete
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Data output format – RGB565,RGB666, RGB888
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DCLK frequency – up to 48 MHz
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HSYNC period (active and blanking)– 1 to 4095 DCLK cycles
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HSYNC pulse width (length of‘inactive’ interval) – 1 to 4095 DCLK cycles
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VSYNC period (active and blanking)– 1 to 4095 HSYNC cycles
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VSYNC pulse width (length of‘inactive’ interval) – 1 to 4095 DCLK cycles
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Active horizontal and verticaldisplay areas – start and end points can each assume a value from 1 to 4095 DCLKs or 1 to 4095 HSYNCs, respectively.
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Front and back horizontal andvertical porches – Start and end points can each assume a value from 1 to 4095 DCLKs or 1 to 4095 HSYNCs, respectively.
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Background color value
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Skew between active VSYNC edge andfirst active HSYNC edge – 0 to 4095 DCLKs
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Polarity ofVSYNC, HSYNC, and DEN
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Launching edge of DCLK
(以下内容来自80-VM155-2MSM7X27A MOBILE STATION MODEM SOFTWARE INTERFACE.pdf)
LCDC registers
MDP_LCDC_EN
0xE0004 MDP_LCDC_HSYNC_CTL
0xE0008 MDP_LCDC_VSYNC_PERIOD
0xE000C MDP_LCDC_VSYNC_PULSE_WIDTH
0xE0010 MDP_LCDC_DISPLAY_HCTL
0xE0014 MDP_LCDC_DISPLAY_V_START
0xE0018 MDP_LCDC_DISPLAY_V_END
0xE001C MDP_LCDC_ACTIVE_HCTL
0xE0020 MDP_LCDC_ACTIVE_V_START
0xE0024 MDP_LCDC_ACTIVE_V_END
0xE0028 MDP_LCDC_BORDER_CLR
0xE002C MDP_LCDC_UNDERFLOW_CTL
0xE0030 MDP_LCDC_HSYNC_SKEW
0xE0034 Reserved
0xE0038 MDP_LCDC_CTL_POLARITY
0xE003C Reserved
0xE0040 Reserved
0xE0044 MDP_LCDC_UFLOW_HIDING_CTL
0xE0048 MDP_LCDC_LOST_PIXEL_CNT_VALUE
对MDP_LCDC_CTL_POLARITY这一寄存器说明
需要注意的是每一位置0表示高电平有效,而非低电平有效。
如果VSYNC,HSYNC, and DEN全部置位0,则相应的timing如下图(全部是在高电平时才能fetchRGB data)
(以下内容来自80-VM155-1MSM7627A-0 AND MSM7227A-0-MSM7227A-1 MOBILE STATION MODEM DEVICESPECIFICATION.pdf)
LCDC timing
SOFTWARE
上面的是硬件相关的介绍,软件控制相应的代码如下:
/kernel/drivers/video/msm/mdp_dma_lcdc.c
intmdp_lcdc_on(struct platform_device *pdev)
{
……
/*
* LCDC timingsetting
*/
MDP_OUTP(MDP_BASE+ timer_base + 0x4, hsync_ctrl);
MDP_OUTP(MDP_BASE+ timer_base + 0x8, vsync_period);
MDP_OUTP(MDP_BASE+ timer_base + 0xc, vsync_pulse_width * hsync_period);
if (timer_base== LCDC_BASE) {
MDP_OUTP(MDP_BASE+ timer_base + 0x10, display_hctl);
MDP_OUTP(MDP_BASE+ timer_base + 0x14, display_v_start);
MDP_OUTP(MDP_BASE+ timer_base + 0x18, display_v_end);
MDP_OUTP(MDP_BASE+ timer_base + 0x28, lcdc_border_clr);
MDP_OUTP(MDP_BASE+ timer_base + 0x2c, lcdc_underflow_clr);
MDP_OUTP(MDP_BASE+ timer_base + 0x30, lcdc_hsync_skew);
MDP_OUTP(MDP_BASE+ timer_base + 0x38, ctrl_polarity);
MDP_OUTP(MDP_BASE+ timer_base + 0x1c, active_hctl);
MDP_OUTP(MDP_BASE+ timer_base + 0x20, active_v_start);
MDP_OUTP(MDP_BASE+ timer_base + 0x24, active_v_end);
……
}