IPC-4921A 中文 CN、IPC-4552B 中文、IPC-6013E 中文 CN、IPC-HDBK-9798,IPC-6018D,IPC-6018DS

IPC-4921A 中文 CN、IPC-4552B 中文、IPC-6013E 中文 CN、IPC-HDBK-9798,IPC-6018D,IPC-6018DS

IPC-4552B 中文 2021 印制板化学镀镍 浸金(ENIG)镀覆性能规范
https://pan.baidu.com/s/12YmmHEeyxY_G24ygz5Bnlw
https://share.weiyun.com/aigOt6Uz


IPC-4921A 中文 CN 印制电子基材(基板)要求(水印版) 
https://pan.baidu.com/s/117OeUPh3LtuuqSIi5sRjEQ
https://share.weiyun.com/SUMM9hN4

IPC-6013E 中文 CN 挠性和刚挠印制板的鉴定性能及规范
https://pan.baidu.com/s/1-NPqIHYxIVDYTHU0EW4cAg
https://share.weiyun.com/2LbYuQN1

IPC-HDBK-9798 Handbook for Press-fit Standard for Automotive Requirements and Other High-
Reliability Applications 汽车要求和其他高可靠性应用的压装标准手册
https://share.weiyun.com/n8ZnbdEx
https://pan.baidu.com/s/1d1dk8Cl3KiKiVl5L6El6gw

IPC-6018D  高频(微波)印制板的鉴定和性能规范
https://pan.baidu.com/s/15ZejLq1iJLV9LZ0cKVCT7g
https://share.weiyun.com/kCGDMp1o


IPC-6018DS 高频(微波)印制板的鉴定及性能规范航天和军事航空电子应用补充标准
https://pan.baidu.com/s/1ynpdRVILQosRoR7gazWR7A
https://share.weiyun.com/iyseSUlh

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MIL-HDBK-217F, Notice 1 is issued to correct minor typographical errors in the basic F Revision. MIL HDBK-217F(base document) provides the following changes based upon recently completed studies (see Ret 30 and 32 listed in Appendix C) 1. New failure rate prediction models are provided for the following nine major classes of microcircuits Monolithic Bipolar Digital and Linear Gate/Logic Array Devices Monolithic MOS Digital and Linear Gate/Logic Array Devices Monolithic Bipolar and MOS Digital Microprocessor Devices(Including Controllers Monolithic Bipolar and Mos Memory Devices Monolithic GaAs Digital Devices Monolithic GaAs MMIC Devices Hybrid Microcircuits Magnetic Bubble Memories Surface Acoustic Wave Devices This revision provides new prediction models for bipolar and Mos microcircuits with gate counts up to 60,000, linear microcircuits with up to 3000 transistors, bipolar and Mos digital microprocessor and co- processors up to 32 bits, memory devices with up to 1 million bits, GaAs monolithic microwave integrated circuits(MMICs)with up to 1,000 active elements, and GaAs digital ICs with up to 10,000 transistors. The C, factors have been extensively revised to reflect new technology devices with improved reliability, and the activation energies representing the temperature sensitivity of the dice(IT)have been changed for MOS devices and for memories. The Ca factor remains unchanged from the previous Handbook version, but includes pin grid arrays and surlace mount packages using the same model as hermetic, solder-sealed dual in-line packages. New values have been included for the quality factor (o), the learning factor(i, and the environmental factor(aE). The model for hybrid microcircuits has been revised to be simpler to use, to delete the temperature dependence of the seal and interconnect fallure rate contributions, and to provide a method of calculating chip junction temperatures 2. A new model for Very High Speed Integrated Circuits(VHSIC/HSIC Like)and very Large Scale Integration(VLSi)devices (gate counts above 60, 000 3. The reformatting of the entire handbook to make i easier to use. 4. A reduction in the number of environmental factors( F)from 27 to 14 5. A revised fallure rate model for Network Resistors 6. Revised models for TWTs and Klystrons based on data supplied by the Electronic Industries Association Microwave Tube Division Supersedes page vil of Revision F A1emn彐TTu"“11r4raeK

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