特权同学verilog边码边学每日记录day1

 今日学习任务：独立的写出超声波测距设计的主模块与子模块

always@(posedge i_clk)
	if(!i_rst_n) r_echo<= 'b0;
	else r_echo <= {r_echo[0],i_echo};
	
	assign pos_echo = ~r_echo[1] & r_echo[0];
	assign neg_echo = r_echo[1] & ~r_echo[0];	

 这个边缘检测代码要记住，很简短