(1)Visio视图:
(2)Verilog代码:
module counter_ten(clk,reset_n,led_out);
input clk;
input reset_n;
output reg led_out;
// 0.5s = 500_000_000ns = 20ns * 25_000_000; 需要25位的寄存器去储存。
reg [24:0] cnt;
reg en_cnt;
reg cnt_flag;
reg [4:0]flag_cnt;
//参数设计
parameter MCNT = 25'd24_999_999;
//计数器模块设计
always@(posedge clk or negedge reset_n)
if(!reset_n)
cnt <= 25'd0;
else if(en_cnt && (cnt == MCNT))
cnt <= 25'd0;
else if(en_cnt)
cnt <= cnt + 25'd1;
else
cnt <= 25'd0;
//标志信号设计
always@(posedge clk or negedge reset_n)
if(!reset_n)
cnt_flag <= 1'd0;
else if(cnt == MCNT - 25'd1)
cnt_flag <= 1'd1;
else
cnt_flag <= 1'd0;
//flag_cnt信号设计
always@(posedge clk or negedge reset_n)
if(!reset_n)
flag_cnt <= 5'd0;
else if (cnt_flag)
flag_cnt <= flag_cnt + 5'd1;
else
flag_cnt <= flag_cnt;
//en_cnt信号设计
always@(posedge clk or negedge reset_n)
if(!reset_n)
en_cnt <= 1'd0;
else if((cnt_flag)&&(flag_cnt == 5'd19))
en_cnt <= 1'd0;
else if(flag_cnt < 5'd20)
en_cnt <= 1'd1;
else
en_cnt <= en_cnt;
//led_out灯翻转设计
always@(posedge clk or negedge reset_n)
if(!reset_n)
led_out <= 1'd0;
else if(cnt_flag)
led_out <= ~led_out;
else
led_out <= led_out;
endmodule
(3)仿真文件代码:
`timescale 1ns/1ns
module counter_tb;
reg clk;
reg reset_n;
wire led_out;
counter_ten counter_ten_inst(
.clk(clk),
.reset_n(reset_n),
.led_out(led_out)
);
defparam counter_ten_inst.MCNT = 25'd24;
initial clk = 1'd1;
always #10 clk = ~clk;
initial begin
reset_n <= 1'd0;
#200;
reset_n <= 1'd1;
#30_000;
$stop;
end
endmodule
(4)仿真波形:
(5)引脚绑定:
set_property IOSTANDARD LVCMOS33 [get_ports led_out]
set_property IOSTANDARD LVCMOS33 [get_ports reset_n]
set_property IOSTANDARD LVCMOS33 [get_ports clk]
set_property PACKAGE_PIN M21 [get_ports led_out]
set_property PACKAGE_PIN N15 [get_ports reset_n]
set_property PACKAGE_PIN W19 [get_ports clk]
#4线spi模式
set_property CFGBVS VCCO [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property BITSTREAM.CONFIG.SPI_BUSWIDTH 4 [current_design]
set_property CONFIG_MODE SPIx4 [current_design]
set_property BITSTREAM.CONFIG.CONFIGRATE 50 [current_design]