NXP LS1046A CPU资源介绍

 

LS1046A 是属于  QorIQ LS series 的一个CPU，它的框图如下：

 1、Four 32/64-bit Arm v8 A72 CPUs

• 每个核的L1 I-Cache （instruction cache）和 L1 D-Cache（data cache）都是独立的。
• 4个核共享L2-Cache 
• up to 1.8Ghz

2、Cache coherent interconnect (CCI-400)

  这个是保证 cache 一致性的，是硬件来操作的，毕竟2M的L2-Cache 是4个核共享的。

3、QorIQ data path acceleration architecture (DPAA)

DPAA 是SOC内部的一个硬件资源，由框图可以看出，它由4个部分组成 FMan QMan BMan SEC。

FMan(Frame Manager) :  Packet parsing, classification, and distribution

QMan(Queue Manger): Queue management for scheduling, packet sequencing, and congestion
management

BMan(Buffer Manager): Hardware buffer management for buffer allocation and de-allocation

SEC(Security Engine): Cryptography acceleration

4、Ethernet interfaces supported by FMan

• Up to two XFI (10 GbE) interface
• Up to five SGMII interface supporting 1000 Mbps
• Up to three SGMII interface supporting 2500 Mbps
• One QSGMII interface
• Supports 10GBase-KR
• Supports 1000Base-KX

5、High-speed peripheral interfaces

• Three PCI express 3.0 controllers, one supporting x4 operation
• One serial ATA (SATA 3.0) controller
 

6、Two Configurable x4 SerDes

• Two PLLs per four-lane SerDes
• Support for 10 GHz operation