EDA与VHDL题目——八选一选择器

EDA与VHDL题目——八选一选择器

代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY mux8 IS
    PORT(data0,data1,data2,data3,data4,data5,data6,data7,a,b,c:IN STD_LOGIC;
         q:OUT STD_LOGIC);
END mux8;
ARCHITECTURE concunt OF mux8 IS
SIGNAL sel:STD_LOGIC_VECTOR(2 DOWNTO 0);
BEGIN
    sel<=c&b&a;
WITH sel SELECT
q<= data0 WHEN "000",
	 data1 WHEN "001",
	 data2 WHEN "010",
	 data3 WHEN "011",
	 data4 WHEN "100",
	 data5 WHEN "101",
	 data6 WHEN "110",
	 data7 WHEN "111",
	   'Z' WHEN OTHERS;
END concunt;