Date: June 30th, 2022
Progress:
fir_system.sv:
- Currently the 'fir_system_0' in platform designer has no connection to data in and data out. The 'mics' logic variable is 'data' channel in platform designer, and 'mics_filtered' is 'data_o'.
- The 'LRCLK' is generated by 'aud_lrclk1', which is an Intel IP 'Audio LR Clock for DE-series Boards'.
- The "software part" of the project is not based on NIOS-II, and there's no NIOS-II block in platform designer. Instead, the 'hps_0' and 'sysid_qsys' could be the possible replacement.
Issue:
- Undetermined software part.
Reflection & Plan:
- Take note of I2S in next blog.
- Figure out the current function of fir_system.
O' ever youthful, O' ever weeping.