EGo1下板_四选一数据选择器
1. 代码
1.1. 功能模块muv4_1
充作顶层文件,在.xdc约束文件中修改分配各个信号在 FPGA 芯片上引脚的位置即可
module mux4_1 (
output reg dout,
input wire a,
input wire b,
input wire c,
input wire d,
input wire [1:0] sel
);
always @ (*) begin
case (sel)
2'b00: dout = a;
2'b01: dout = b;
2'b10: dout = c;
2'b11: dout = d;
default: dout = 1'b0;
endcase
end
endmodule
1.2. 测试模块muv4_1_tb
module mux4_1_tb;
wire dout;
reg a, b, c, d;
reg [1:0]sel;
mux4_1 u1(.dout(dout), .a(a), .b(b), .c(c), .d(d), .sel(sel));
initial
begin
a = 0;
b = 0;
c = 0;
d = 0;
sel = 2'b00;
#10 a = 1;
#10 a = 0;
#10 a = 1;
#10 a = 0;
sel = 2'b01;
#10 b = 1;
#10 b = 0;
#10 b = 1;
#10 b = 0;
sel = 2'b10;
#10 c = 1;
#10 c = 0;
#10 c = 1;
#10 c = 0;
sel = 2'b11;
#10 d = 1;
#10 d = 0;
#10 d = 1;
#10 d = 0;
end
endmodule
2. Vivado下板过程
2.1. 仿真测试
“Flow Navigator” -> “Simulation” -> “Run Simulation” -> “Run Behavior Simulation”
2.2. 添加约束文件.xdc
set_property -dict {PACKAGE_PIN P5 IOSTANDARD LVCMOS33} [get_ports {a}]
set_property -dict {PACKAGE_PIN P4 IOSTANDARD LVCMOS33} [get_ports {b}]
set_property -dict {PACKAGE_PIN P3 IOSTANDARD LVCMOS33} [get_ports {c}]
set_property -dict {PACKAGE_PIN P2 IOSTANDARD LVCMOS33} [get_ports {d}]
set_property -dict {PACKAGE_PIN N4 IOSTANDARD LVCMOS33} [get_ports {sel[1]}]
set_property -dict {PACKAGE_PIN R1 IOSTANDARD LVCMOS33} [get_ports {sel[0]}]
set_property -dict {PACKAGE_PIN F6 IOSTANDARD LVCMOS33} [get_ports {dout}]
2.3. 综合
“Flow Navigator” -> “Synthesis” -> “Run Synthesis”
2.4. 实现
“Flow Navigator”-> “Implementation” -> “Run Implementation”
2.5. 生成bit文件
“Flow Navigator” -> “Program and Debug” -> “Generate Bitstream”
2.6. 连接
“Hardware Manager” -> “Open target”-> “Auto Connect”
2.7. 下载
在目标芯片上右击,选择 “Program Device”
3. 下板结果
SW[0:3]: a, b, c, d
SW[6:7]: sel
4. 遇到的问题
- 实现之后,生成bit流阶段断开板子电源,提示报错
打开板子开关,重新实现,在生成二进制文件就好了 - 下载的时候提示报错,
[Labtoolstcl 44-494] There is no active target available for server at localhost. Targets(s) “, jsn1” may be locked by another hw_server.
百度看到一种方法,先关掉localhost(0),然后重新auto connect,就可以通过
我也这样尝试过,结果不行,后来发现是板子没有上电,上电之后重新下载就好了