结构如图所示:
抛开时钟和复位信号,结合题目叙述,这里的模块就很清晰
代码:
`timescale 1ns/1ns
module game_count
(
input rst_n, //异位复位信号,低电平有效
input clk, //时钟信号
input [9:0]money,
input set,
input boost,
output reg[9:0]remain,
output reg yellow,
output reg red
);
always @(posedge clk or negedge rst_n)begin
if(~rst_n)begin
remain <= 9'b0;
end
else begin
if(set == 1)begin
remain <= money+remain;
end
else begin
if(remain == 0)
remain <= 0;
else if(boost == 0 )
remain <= remain - 1;
else if(boost == 1 )
remain <= remain -2;
end
end
end
always @(posedge clk or negedge rst_n)begin
if(~rst_n)begin
yellow <= 0;
red <= 1;
end
else begin
if(remain >1 &&remain <=10 )begin
yellow <= 1;
red <=0;
end
else if(remain<=1 &&boost == 1)begin
red <=1;
yellow <= 0;
end
else if(remain==0 && boost == 0)begin
yellow <= 0;
red <=1;
end
else begin
yellow <= 0;
red <= 0;
end
end
end
endmodule
测试
`timescale 1ns/1ns
module testbench();
reg clk,rst_n;
reg set,boost;
reg [9:0]money;
wire red,yellow;
wire [9:0]remain;
real CYCLE_50MHz = 20 ;
always begin
clk = 0 ; #(CYCLE_50MHz/2) ;
clk = 1 ; #(CYCLE_50MHz/2) ;
end
initial begin
rst_n = 0;set = 0;boost = 0; #20;
rst_n = 1; #20;
money = 9'd15;set = 1;#20;
set = 0;#320;
money = 9'd50;set = 1;#20;
set = 0;#200;
boost = 1 ;#200;
money = 9'd20;set = 1;#20;
set = 0;#850;
$stop;
end
game_count dut
(
.rst_n(rst_n),
.clk(clk),
.set(set),
.money(money),
.boost(boost),
.red(red),
.yellow(yellow),
.remain(remain)
);
endmodule