fsmc testbench

`timescale 1ns/1ps
module testbench ();
reg clk;
reg rst_n;

reg SCLK;

reg ready;

wire mcu_flag;

wire data0;

reg [7:0] count;
reg [7:0] ADC_dat_reg;
reg [7:0] memory[0:77];
reg [7:0] count_cnt;
reg mcu_pul_r;
integer i;
reg flag;
reg ready_r;
reg[7:0] n;
reg[7:0] read_data;
reg int_flag;
//****************************
wire [7:0] fsmc_dat;
reg fsmc_cs;
reg fsmc_rs;
reg fsmc_wr;
reg fsmc_rd;
reg [7:0] fsmc_dat_reg;

assign data0=(count_cnt>8’d8&&flag)?ADC_dat_reg[7]:1’b1;

assign fsmc_dat=fsmc_rd?fsmc_dat_reg:8’hzz;//cui

GSR GSR(.GSRI(1’b1));

initial begin
$readmemh(“file.txt”,memory);
for(i=0;i<=12;i=i+1)
$display("%h",memory[i]);
end

initial begin
clk=0;
rst_n=0;
SCLK=0;
ready=0;
ADC_dat_reg=8’d0;
flag=0;
int_flag=0;
n=0;
ready=0;
#20 rst_n=1;
#56000;
FSMC_write_cmd(8’h51);
FSMC_write_data(8’haa);
FSMC_write_data(8’h55);
FSMC_write_data(8’h00);
FSMC_write_data(8’h01);
#5000;
int_flag=1;
#50;
int_flag=0;
wait(mcu_flag);
repeat(12)begin
FSMC_rd_data(fsmc_dat,read_data);
end
end

always #10 clk=!clk;
always #50 SCLK=!SCLK;

task FSMC_write_cmd;
input [7:0] data;
begin
fsmc_cs=0;
fsmc_wr=0;
fsmc_rd=1;
fsmc_rs=1;
fsmc_dat_reg=8’d0;
#50;
fsmc_cs=0;
fsmc_rd=1;
fsmc_rs=1;
fsmc_wr=1;
fsmc_dat_reg=data;
#50;
fsmc_cs=0;
fsmc_rd=1;
fsmc_rs=0;
fsmc_wr=0;
fsmc_dat_reg=8’d0;

end
endtask

task FSMC_write_data;
input [7:0] data;
begin
fsmc_cs=0;
fsmc_wr=0;
fsmc_rd=1;
fsmc_rs=0;
fsmc_dat_reg=8’d0;
#50;
fsmc_cs=0;
fsmc_rd=1;
fsmc_rs=0;
fsmc_wr=1;
fsmc_dat_reg=data;
#50;
fsmc_cs=0;
fsmc_rd=1;
fsmc_rs=0;
fsmc_wr=0;
fsmc_dat_reg=8’d0;

end
endtask

task FSMC_rd_data;
input [7:0] data;
output [7:0] rd_data;
begin
fsmc_cs=0;
fsmc_wr=1;
fsmc_rd=0;
fsmc_rs=0;
#50;
fsmc_cs=0;
fsmc_rd=1;
fsmc_rs=0;
fsmc_wr=1;
#50 rd_data=data;
#50;
fsmc_cs=0;
fsmc_rd=0;
fsmc_rs=0;
fsmc_wr=1;
end
endtask

endmodule

fsmc testbemch