verilog有符号加法

本模块默认以补码的形式输入有符号数
tb:

`timescale 1ns/1ps
module name ();
reg clk;
reg rst_n;
reg [3:0] data_in;
reg data_vld_in;
wire [5:0] data_o;
wire 	   data_vld_o;

initial
begin 
clk=0;
rst_n=0;
#200;
rst_n=1;
end

always #10 clk=~clk;

initial
begin 
data_in=4'd0;
data_vld_in=0;
#500;
send(-4'd2);
send(4'd1);
send(-4'd1);
send(4'd1);
end

task send;
	input[3:0] data;
	begin
	data_in=data;
	@(negedge clk)
	begin
	data_vld_in=1;
	end
	@(negedge clk)
	begin
	data_vld_in=0;
	end
	#50;
	end
endtask

signed_add signed_add(
	.clk(clk),
	.rst_n(rst_n),
	.data_in(data_in),
	.data_vld_in(data_vld_in),
	.data_o(data_o),
	.data_vld_o(data_vld_o)
	);

endmodule

verilog:

//默认给进来的数就是补码形式的
module signed_add (
	input 			clk,    // Clock
	input 			rst_n,  // Asynchronous reset active low
	input 	  [3:0] data_in,
	input 			data_vld_in,
	output wire[5:0] data_o,
	output reg 	data_vld_o
);
reg [3:0] data_in_reg;
reg 	  vld_reg;
always @(posedge clk or negedge rst_n) begin
	if(~rst_n) begin
		 data_in_reg<= 0;
		 vld_reg    <= 0;
	end else begin
		 data_in_reg<= data_in;
		 vld_reg  	<= data_vld_in;
	end
end

reg[1:0] data_cnt;
always @(posedge clk or negedge rst_n) begin
	if(~rst_n)
		 data_cnt<= 0;
	else if(vld_reg)
		 data_cnt<= data_cnt+1 ;
	else
		 data_cnt<=data_cnt;
end

reg[5:0] data_o_reg;
always @(posedge clk or negedge rst_n) begin
	if(~rst_n)
		 data_o_reg<= 0;
	// else if(data_cnt==2'd0)
	// 	 data_o_reg<={{2{data_in_reg[3]}},data_in_reg[3:0]};
	else if (vld_reg)
		 data_o_reg<=data_o_reg+{{2{data_in_reg[3]}},data_in_reg[3:0]};
end

always @(posedge clk or negedge rst_n) begin
	if(~rst_n)
		 data_vld_o<= 0;
	else if(data_cnt==2'd3&&vld_reg)
		 data_vld_o<= 1;
	else
		 data_vld_o<= 0;
end

assign data_o=(data_cnt==2'd0)?data_o_reg:6'd0;


endmodule

波形图：