Uart Rx模块封装成AXI Master

模块介绍

之前已经介绍了Uart 收发模块，并将Rx与Tx模块连接来进行回环验证。其中Rx模块由Uart_rx与speed_set构成，这里我们将Rx模块封装成AXI总线形式，当成AXI Master写数据给Ram/FIFO Slave。

本模快例化Rx模块，Rx模块将数据串转并输入到Mater的M_AXI_WDATA端口。因为本模块只是实现将Rx接受数据写入到Ram（Ram Slave）中，所以Matser只是实现写控制，并没有读功能。Master中写Transaction中包含三个通道，分别为写地址、写数据及写反响应。各通道均采用Valid与Ready信号握手协议来进行控制。

代码实现

`timescale 1ns / 1ps
//
// Company: 
// Engineer: 
// 
// Create Date: 2019/06/18 15:32:36
// Design Name: 
// Module Name: M_AXI_Rx
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//

module M_AXI_Rx #(
	// Width of S_AXI data bus
	parameter integer C_M_AXI_DATA_WIDTH	= 8,
	// Width of S_AXI address bus
	parameter integer C_M_AXI_ADDR_WIDTH	= 8
)
(		
		input wire  M_AXI_ACLK,
		input wire  M_AXI_ARESETN,
		output ERROR,
		
		// AXI write address channel
		input wire  M_AXI_AWREADY,
		output wire M_AXI_AWVALID,			
		output wire [C_M_AXI_ADDR_WIDTH-1 : 0] M_AXI_AWADDR,
		
		// AXI write data channel
		output wire [C_M_AXI_DATA_WIDTH-1 : 0] M_AXI_WDATA,
		output wire  M_AXI_WVALID,
		input wire  M_AXI_WREADY,
		
		//AXI write response channel
		input wire [1 : 0] M_AXI_BRESP,
		input wire  M_AXI_BVALID,
		output wire  M_AXI_BREADY,
		
		//Users to add ports 
		input Rx
		
		
);

//----------------------AXI4LITE signals--------------------------------
	reg  	axi_awvalid;
	reg [C_M_AXI_ADDR_WIDTH-1 : 0] 	axi_awaddr;	
	reg [C_M_AXI_DATA_WIDTH-1 : 0] 	axi_wdata;
	reg  	axi_wvalid;	
	reg  	axi_bready;	
	
	//A pulse to initiate a write transaction
	reg  	start_single_write;
	//Asserts when a single beat write transaction is issued and remains asserted till the completion of write trasaction.
	reg  	write_issued;
	reg  	init_txn_ff;
	reg  	init_txn_ff2;
	wire  	init_txn_pulse;
	
	wire [7:0] rx_data;
	wire rx_int;
    wire bps_start_rx;
    wire bps_clk_rx;
    
    parameter [1:0] IDLE = 2'b00, // This state initiates AXI4Lite transaction 
                // after the state machine changes state to INIT_WRITE   
                // when there is 0 to 1 transition on INIT_AXI_TXN
            INIT_WRITE   = 2'b01