Verilog语言 HDLBits_1

Getting Start:

1. Build a circuit with no inputs and one output. That output should always drive 1 (or logic high).

module top_module( output one );

// Insert your code here
    assign one = 1;

endmodule

2. Build a circuit with no inputs and one output that outputs a constant 0

module top_module(
    output zero
);// Module body starts after semicolon
	assign zero = 0;
endmodule

Fun fact: For Quartus synthesis, not assigning a value to a signal usually results in 0. This problem is actually easier than the previous one.

Basics:

1. Create a module with one input and one output that behaves like a wire.

module top_module( input in, output out );
	assign out = in;
endmodule

2. Create a module with 3 inputs and 4 outputs that behaves like wires that makes these connections:
   a -> w; b -> x; b -> y; c -> z

module top_module( 
    input a,b,c,
    output w,x,y,z );
	assign w = a;
    assign x = b;
    assign y = b;
    assign z = c;
endmodule

3. Create a module that implements a NOT gate.

module top_module( input in, output out );
	assign out = !in;
endmodule

4. Create a module that implements an AND gate.

module top_module( 
    input a, 
    input b, 
    output out );
	assign out = a & b;
endmodule

5. Create a module that implements a NOR gate. A NOR gate is an OR gate with its output inverted. A NOR function needs two operators when written in Verilog.

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = !(a | b);
endmodule

6. Create a module that implements an XNOR gate.

module top_module( 
    input a, 
    input b, 
    output out );
    assign out = !(a^b);
endmodule

Declaring wires
The circuits so far have been simple enough that the outputs are simple functions of the inputs. As circuits become more complex, you will need wires to connect internal components together. When you need to use a wire, you should declare it in the body of the module, somewhere before it is first used. (In the future, you will encounter more types of signals and variables that are also declared the same way, but for now, we’ll start with a signal of type wire).

module top_module (
    input in,              // Declare an input wire named "in"
    output out             // Declare an output wire named "out"
);

    wire not_in;           // Declare a wire named "not_in"

    assign out = ~not_in;  // Assign a value to out (create a NOT gate).
    assign not_in = ~in;   // Assign a value to not_in (create another NOT gate).

endmodule   // End of module "top_module"

`default_nettype none
module top_module(input a,input b,input c,input d,output out,output out_n   ); 
	wire anb,cnd;
    assign anb = a&b;
    assign cnd = c&d;
    assign out = anb|cnd;
    assign out_n = !out;
endmodule

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );
	wire w1,w2,w3,w4;
    assign w1 = p2a&p2b;
    assign w2 = p2c&p2d;
    assign p2y = w1|w2;
    assign w3 = p1c&p1a&p1b;
    assign w4 = p1f&p1e&p1d;
    assign p1y = w3|w4;
endmodule