在产生内核时，翻译了一个小小的说明文件

本地地址：E:/FPGA/vedio/fifo/myfifo_readme.txt

The following files were generated for 'myfifo' in directory                下面的文件是由“myfifo”产生的，所在目录：
E:/FPGA/vedio/fifo:                                                         E:/FPGA/vedio/fifo:

myfifo.asy:                                                                 myfifo.asy:
   Graphical symbol information file. Used by the ISE tools and some        图形符号信息文件。被ISE工具和其他第三方工具使用来建立一个符号描述内核。
   third party tools to create a symbol representing the core.

myfifo.ngc:                                                                 myfifo.ngc:
   Binary Xilinx implementation netlist file containing the information     二进制的Xilinx实现网表文件包含在XilinxFPGA上的模块实现的信息。
   required to implement the module in a Xilinx (R) FPGA.

myfifo.sym:                                                                 myfifo.sym:
   Please see the core data sheet.                                          请看内核的文档

myfifo.v:                                                                   myfifo.v:
   Verilog wrapper file provided to support functional simulation.          提供功能性仿真的Verilog封装文件。这个文件包含仿真的模型客制数据,这个数据用来给内核传递参数化数据   

This file contains simulation model customization data that is            
   passed to a parameterized simulation model for the core.

myfifo.veo:                                                                 myfifo.veo:
   VEO template file containing code that can be used as a model for        VEO模板文件包含能够被用在模块上来在Verilog设计中来示例一个内核产生器模块的代码。
   instantiating a CORE Generator module in a Verilog design.

myfifo.vhd:                                                                 myfifo.vhd:
   VHDL wrapper file provided to support functional simulation. This        VHDL封装文件提供提供支持功能性仿真。这个文件包含仿真的模型客制数据,这个数据用来给内核传递参数化数据
   file contains simulation model customization data that is passed to
   a parameterized simulation model for the core.

myfifo.vho:                                                                 myfifo.vho:
   VHO template file containing code that can be used as a model for        VHO模板文件包含能够用来在VHDL设计中示例一个内核发生器的模块代码。
   instantiating a CORE Generator module in a VHDL design.

myfifo.xco:                                                                 myfifo.xco:
   CORE Generator input file containing the parameters used to              内核产生器输入文件包含用来重写一个内核的参数。
   regenerate a core.

myfifo_fifo_generator_v3_3_xst_1_vhdl.prj:                                  myfifo_fifo_generator_v3_3_xst_1_vhdl.prj:
   Please see the core data sheet.                                          请看相关的文档

myfifo_flist.txt:                                                           myfifo_flist.txt:
   Text file listing all of the output files produced when a customized     纯文本文件列举了在内核产生器产生一个客制化的内核产生的所有输出文件。
   core was generated in the CORE Generator.

myfifo_readme.txt:                                                          myfifo_readme.txt:
   Text file indicating the files generated and how they are used.          纯文本文件指出了产生的文件的使用。

myfifo_xmdf.tcl:                                                            myfifo_xmdf.tcl:
   Please see the core data sheet.                                          请看相关的文档


Please see the Xilinx CORE Generator online help for further details on     欲了解更多的关于产生的文件以及用途，请看Xilinx内核产生器的在线帮助。
generated files and how to use them.